Datasheet

DP83849IF

SNOSAX8D –JUNE 2009–REVISED APRIL 2013

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When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the

transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is

generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of

the MII.

6.1.3 Carrier Sense

Carrier Sense (CRS) is asserted due to receive activity, once valid data is detected via the squelch

function during 10 Mb/s operation. During 100 Mb/s operation CRS is asserted when a valid link (SD) and

two non-contiguous zeros are detected on the line.

For 10 or 100 Mb/s Half Duplex operation, CRS is asserted during either packet transmission or reception.

For 10 or 100 Mb/s Full Duplex operation, CRS is asserted only due to receive activity.

CRS is deasserted following an end of packet.

6.2 REDUCED MII INTERFACE

The DP83849IF incorporates the Reduced Media Independent Interface (RMII) as specified in the RMII

specification (rev1.2) from the RMII Consortium. This interface may be used to connect PHY devices to a

MAC in 10/100 Mb/s systems using a reduced number of pins. In this mode, data is transferred 2-bits at a

time using the 50 MHz RMII_REF clock for both transmit and receive. The following pins are used in RMII

mode:

• TX_EN

• TXD[1:0]

• RX_ER (optional for MAC)

• CRS_DV

• RXD[1:0]

• X1 (RMII Reference clock is 50 MHz)

In addition, the RMII mode supplies an RX_DV signal which allows for a simpler method of recovering

receive data without having to separate RX_DV from the CRS_DV indication. This is especially useful for

diagnostic testing where it may be desirable to externally loop Receive MII data directly to the transmitter.

The RX_ER output may be used by the MAC to detect error conditions. It is asserted for symbol errors

received during a packet, False Carrier events, and also for FIFO underrun or overrun conditions. Since

the Phy is required to corrupt receive data on an error, a MAC is not required to use RX_ER.

It is important to note that since both digital channels in the DP83849IF share the X1/RMII_REF input,

both channels must have RMII mode enabled or both channels must have RMII mode disabled. Either

channel may be in 10Mb or 100Mb mode in RMII or non-RMII mode.

Since the reference clock operates at 10 times the data rate for 10 Mb/s operation, transmit data is

sampled every 10 clocks. Likewise, receive data will be generated every 10th clock so that an attached

device can sample the data every 10 clocks.

RMII mode requires a 50 MHz oscillator be connected to the device X1 pin. A 50 MHz crystal is not

supported.

To tolerate potential frequency differences between the 50 MHz reference clock and the recovered receive

clock, the receive RMII function includes a programmable elasticity buffer. The elasticity buffer is

programmable to minimize propagation delay based on expected packet size and clock accuracy. This

allows for supporting a range of packet sizes including jumbo frames.

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