Datasheet
DP83849IF
www.ti.com
SNOSAX8D –JUNE 2009–REVISED APRIL 2013
1 Introduction .............................................. 1 4.23 AC Specifications — 10 Mb/s Heartbeat Timing ... 24
1.1 Features ............................................. 1 4.24 AC Specifications — 10 Mb/s Jabber Timing ...... 24
4.25 AC Specifications — 10BASE-T Normal Link Pulse
1.2 Applications .......................................... 1
Timing .............................................. 25
1.3 Description ........................................... 2
4.26 AC Specifications — Auto-Negotiation Fast Link
2 Device Information ...................................... 5
Pulse (FLP) Timing ................................. 25
2.1 System Diagram ..................................... 5
4.27 AC Specifications — 100BASE-TX Signal Detect
2.2 Block Diagram ....................................... 5
Timing .............................................. 25
3 Pin Descriptions ......................................... 6
4.28 AC Specifications — 100 Mb/s Internal Loopback
Timing .............................................. 26
3.1 Connection Diagram ................................. 7
4.29 AC Specifications — 10 Mb/s Internal Loopback
3.2 PACKAGE PIN ASSIGNMENTS .................... 8
Timing .............................................. 27
3.3 SERIAL MANAGEMENT INTERFACE .............. 9
4.30 AC Specifications — RMII Transmit Timing ........ 27
3.4 MAC DATA INTERFACE ............................ 9
4.31 AC Specifications — RMII Receive Timing ........ 28
3.5 CLOCK INTERFACE ............................... 10
4.32 AC Specifications — Single Clock MII (SCMII)
3.6 LED INTERFACE .................................. 10
Transmit Timing .................................... 29
3.7 JTAG INTERFACE ................................. 11
4.33 AC Specifications — Single Clock MII (SCMII)
3.8 RESET AND POWER DOWN ...................... 11
Receive Timing ..................................... 29
3.9 STRAP OPTIONS .................................. 11
4.34 AC Specifications — Isolation Timing .............. 30
3.10 10 Mb/s AND 100 Mb/s PMD INTERFACE ........ 13
4.35 AC Specifications — CLK2MAC Timing ............ 30
3.11 SPECIAL CONNECTIONS ......................... 13 4.36 AC Specifications — 100 Mb/s X1 TO TX_CLK
Timing .............................................. 30
3.12 POWER SUPPLY PINS ............................ 13
5 Configuration ........................................... 31
4 Electrical Specifications ............................. 14
5.1 MEDIA CONFIGURATION ......................... 31
4.1 Absolute Maximum Ratings ........................ 14
5.2 AUTO-NEGOTIATION .............................. 31
4.2 Recommended Operating Conditions .............. 14
5.3 AUTO-MDIX ........................................ 34
4.3 AC and DC Specifications .......................... 14
5.4 PHY ADDRESS .................................... 34
4.4 DC Specifications .................................. 15
5.5 LED INTERFACE ................................... 35
4.5 AC Specifications — Power Up Timing ............ 16
5.6 HALF DUPLEX vs. FULL DUPLEX ................ 37
4.6 AC Specifications — Reset Timing ................. 17
5.7 INTERNAL LOOPBACK ............................ 37
4.7 AC Specifications — MII Serial Management Timing
...................................................... 18
5.8 BIST ................................................ 37
4.8 AC Specifications — 100 Mb/s MII Transmit Timing
6 MAC Interface .......................................... 39
...................................................... 18
6.1 MII INTERFACE .................................... 39
4.9 AC Specifications — 100 Mb/s MII Receive Timing 18
6.2 REDUCED MII INTERFACE ....................... 40
4.10 AC Specifications — 100BASE-TX and 100BASE-
6.3 10 Mb SERIAL NETWORK INTERFACE (SNI) .... 41
FX MII Transmit Packet Latency Timing ........... 19
6.4 SINGLE CLOCK MII MODE ........................ 41
4.11 AC Specifications — 100BASE-TX and 100BASE-
6.5 FLEXIBLE MII PORT ASSIGNMENT .............. 42
FX MII Transmit Packet Deassertion Timing ....... 19
6.6 802.3u MII SERIAL MANAGEMENT INTERFACE . 45
4.12 AC Specifications — 100BASE-TX Transmit Timing
(t
R/F
& Jitter) ........................................ 20
7 Architecture ............................................. 48
4.13 AC Specifications — 100BASE-TX and 100BASE-
7.1 100BASE-TX TRANSMITTER ...................... 48
FX MII Receive Packet Latency Timing ............ 20
7.2 100BASE-TX RECEIVER .......................... 50
4.14 AC Specifications — 100BASE-TX and 100BASE-
7.3 100BASE-FX OPERATION ......................... 55
FX MII Receive Packet Deassertion Timing ....... 21
7.4 10BASE-T TRANSCEIVER MODULE .............. 55
4.15 AC Specifications — 10 Mb/s MII Transmit Timing 21
8 Design Guidelines ..................................... 59
4.16 AC Specifications — 10 Mb/s MII Receive Timing . 21
8.1 TPI NETWORK CIRCUIT .......................... 59
4.17 AC Specifications — 10 Mb/s Serial Mode Transmit
Timing .............................................. 22 8.2 FIBER NETWORK CIRCUIT ....................... 60
4.18 AC Specifications — 10 Mb/s Serial Mode Receive
8.3 ESD PROTECTION ................................ 60
Timing .............................................. 22
8.4 CLOCK IN (X1) REQUIREMENTS ................. 61
4.19 AC Specifications — 10BASE-T Transmit Timing
8.5 POWER FEEDBACK CIRCUIT .................... 63
(Start OF Packet) ................................... 22
8.6 POWER DOWN/INTERRUPT ...................... 63
4.20 AC Specifications — 10BASE-T Transmit Timing
8.7 ENERGY DETECT MODE ......................... 64
(End of Packet) ..................................... 23
8.8 LINK DIAGNOSTIC CAPABILITIES ................ 64
4.21 AC Specifications — 10BASE-T Receive Timing
(Start of Packet) .................................... 23
9 Reset Operation ........................................ 69
4.22 AC Specifications — 10BASE-T Receive Timing
9.1 HARDWARE RESET ............................... 69
(End of Packet) ..................................... 24
9.2 FULL SOFTWARE RESET ......................... 69
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