Datasheet

T.2.15.2
T2.15.1
TX_CLK
TX_EN
TXD
Valid Data
T2.14.1T2.14.1
T2.14.2
RX_CLK
RXD[0]
RX_DV
TX_CLK
Valid Data
T2.13.3 T2.13.4
T2.13.1 T2.13.2
DP83849IF
SNOSAX8D –JUNE 2009–REVISED APRIL 2013 www.ti.com
4.17 AC Specifications — 10 Mb/s Serial Mode Transmit Timing
Parameter Description Notes Min Typ Max Units
T2.13.1 TX_CLK High Time 10 Mb/s Serial mode 20 25 30 ns
T2.13.2 TX_CLK Low Time 10 Mb/s Serial mode 70 75 80 ns
T2.13.3 TXD_0, TX_EN Data Setup to 10 Mb/s Serial mode 25 ns
TX_CLK rise
T2.13.4 TXD_0, TX_EN Data Hold from 10 Mb/s Serial mode 0 ns
TX_CLK rise
4.18 AC Specifications — 10 Mb/s Serial Mode Receive Timing
(1)
Parameter Description Notes Min Typ Max Units
T2.14.1 RX_CLK High/Low Time 35 50 65 ns
T2.14.2 RX_CLK fall to RXD_0, RX_DV Delay 10 Mb/s Serial mode -10 10 ns
(1) RX_CLK may be held high for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
4.19 AC Specifications — 10BASE-T Transmit Timing (Start OF Packet)
(1)
Parameter Description Notes Min Typ Max Units
T2.15.1 Transmit Output Delay from the 10 Mb/s MII mode 3.5 bits
Falling Edge of TX_CLK
T2.15.2 Transmit Output Delay from the 10 Mb/s Serial mode 3.5 bits
Rising Edge of TX_CLK
(1) 1 bit time = 100 ns in 10Mb/s.
22 Electrical Specifications Copyright © 2009–2013, Texas Instruments Incorporated
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