Datasheet

T2.12.1
T2.12.3T2.12.2
Valid Data
RX_CLK
RXD[3:0]
RX_DV
T2.12.1
T2.11.1 T2.11.1
T2.11.2
T2.11.3
Valid Data
TX_CLK
TXD[3:0]
TX_EN
IDLE(T/R)DATA
T2.10.1
CRS
PMD Input Pair
DP83849IF
www.ti.com SNOSAX8D –JUNE 2009–REVISED APRIL 2013
4.14 AC Specifications — 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion
Timing
(1)
Parameter Description Notes Min Typ Max Units
T2.10.1 Carrier Sense OFF Delay
(2)
100BASE-TX mode 24 bits
100BASE-FX mode 14
(1) 1 bit time = 10 ns in 100 Mb/s mode.
(2) Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
4.15 AC Specifications — 10 Mb/s MII Transmit Timing
(1)
Parameter Description Notes Min Typ Max Units
T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns
T2.11.2 TXD[3:0], TX_EN Data Setup to 10 Mb/s MII mode 25 ns
TX_CLK fall
T2.11.3 TXD[3:0], TX_EN Data Hold from 10 Mb/s MII mode 0 ns
TX_CLK rise
(1) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on
the falling edge of TX_CLK.
4.16 AC Specifications — 10 Mb/s MII Receive Timing
(1)
Parameter Description Notes Min Typ Max Units
T2.12.1 RX_CLK High/Low Time 160 200 240 ns
T2.12.2 RX_CLK TO RXD[3:0}, RX_DV Delay 10 Mb/s MII mode 100 ns
T2.12.3 RX_CLK rising edge delay from 10 Mb/s MII mode 100 ns
RXD[3:0], RX_DV Valid
(1) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
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