Datasheet

TX_CLK
TX_EN
TXD
PMD Output
Pair
IDLE DATA(J/K)
T2.7.1
TX_CLK
TX_EN
TXD
PMD Output
Pair
IDLE DATA(J/K)
T2.6.1
DP83849IF
www.ti.com SNOSAX8D –JUNE 2009–REVISED APRIL 2013
4.10 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Latency
Timing
(1)
Parameter Description Notes Min Typ Max Units
T2.6.1 TX_CLK to PMD Output Pair Latency 100BASE-TX and 100BASE-FX modes 5 bits
(1) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
4.11 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Deassertion
Timing
(1)
Parameter Description Notes Min Typ Max Units
T2.7.1 TX_CLK to PMD Output Pair Deassertion 100BASE-TX and 100BASE-FX modes 5 bits
(1) Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the
first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
Copyright © 2009–2013, Texas Instruments Incorporated Electrical Specifications 19
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