Datasheet

DP83849IF

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SNOSAX8D –JUNE 2009–REVISED APRIL 2013

3.7 JTAG INTERFACE

Signal Name Type Pin # Description

TCK I, PU 72 TEST CLOCK

This pin has a weak internal pullup.

TDO O 73 TEST OUTPUT

TMS I, PU 74 TEST MODE SELECT

This pin has a weak internal pullup.

TRSTN I, PU 75 TEST RESET Active low test reset.

This pin has a weak internal pullup.

TDI I, PU 76 TEST DATA INPUT

This pin has a weak internal pullup.

3.8 RESET AND POWER DOWN

Signal Name Type Pin # Description

RESET_N I, PU 71 RESET: Active Low input that initializes or re-initializes the DP83849IF. Asserting

this pin low for at least 1 µs will force a reset process to occur. All internal registers

will re-initialize to their default states as specified for each bit in the Register Block

section. All strap options are re-initialized as well.

PWRDOWN_INT_A I, PU 18 The default function of this pin is POWER DOWN.

PWRDOWN_INT_B 44 POWER DOWN: The pin is an active low input in this mode and should be

asserted low to put the device in a Power Down mode.

INTERRUPT: The pin is an open drain output in this mode and will be asserted low

when an interrupt condition occurs. Although the pin has a weak internal pull-up,

some applications may require an external pull-up resister. Register access is

required for the pin to be used as an interrupt mechanism. See Section 8.6.2 for

more details on the interrupt mechanisms.

3.9 STRAP OPTIONS

The DP83849IF uses many of the functional pins as strap options. The values of these pins are sampled

during reset and used to strap the device into specific modes of operation. The strap option pin

assignments are defined below. The functional pin name is indicated in parentheses.

A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default

option is required, then there is no need for external pull-up or pull down resistors. Since these pins may

have alternate functions after reset is deasserted, they should not be connected directly to V

or GND.

Signal Name Type Pin # Description

PHYAD1 (RXD0_A) S, O, PD 4 PHY ADDRESS [4:1]: The DP83849IF provides four PHY address pins, the state of

PHYAD2 (RXD1_A) S, O, PD 5 which are latched into the PHYCTRL register at system Hardware-Reset. Phy

PHYAD3 (RXD0_B) S, O, PD 58 Address[0] selects between ports A and B.

PHYAD4 (RXD1_B) S, O, PD 57 The DP83849IF supports PHY Address strapping for Port A even values 0 (<0000_0>)

through 30 (<1111_0>). Port B will be strapped to odd values 1 (<0000_1>) through 31

(<1111_1>).

PHYAD[4:1] pins have weak internal pull-down resistors.

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