Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - transceivers Ethernet 2/2 TQFP 80

DP83849IF

www.ti.com

SNOSAX8D –JUNE 2009–REVISED APRIL 2013

DP83849IF PHYTER™ DUAL Industrial Temperature with Fiber Support (FX) and Flexible

Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Tranceiver

Check for Samples: DP83849IF

1 Introduction

• IEEE 802.3u MII

1.1 Features

• IEEE 802.3u Auto-Negotiation and Parallel

123

• Low-Power 3.3V, 0.18µm CMOS Technology

Detection

• Low Power Consumption <600mW Typical

• IEEE 802.3u ENDEC, 10BASE-T Transceivers

• 3.3V MAC Interface

and Filters

• Auto-MDIX for 10/100 Mb/s

• IEEE 802.3u PCS, 100BASE-TX Transceivers

• Energy Detection Mode

and Filters

• Flexible MII Port Assignment

• IEEE 802.3u 100BASE-FX Fiber Interface

• Dynamic Integrity Utility

• IEEE 1149.1 JTAG

• Dynamic Link Quality Monitoring

• Integrated ANSI X3.263 Compliant TP-PMD

Physical Sub-Layer with Adaptive Equalization

• TDR based Cable Diagnostic and Cable Length

and Baseline Wander Compensation

Detection

• Programmable LED Support for Link, 10 /100

• Optimized Latency for Real Time Ethernet

Mb/s Mode, Activity, Duplex and Collision

Operation

Detect

• Reference Clock Out

• Single Register Access for Complete PHY

• RMII Rev. 1.2 Interface (Configurable)

Status

• SNI Interface (Configurable)

• 10/100 Mb/s Packet BIST (Built in Self Test)

• MII Serial Management Interface (MDC and

• 80-pin TQFP Package (12mm x 12mm)

MDIO)

1.2 Applications

• Medical Instrumentation

• Factory Automation

• Motor & Motion Control

• Wireless Remote Base Station

• General Embedded Applications

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PHYTER is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (104 pages)

PAGE 1
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 DP83849IF PHYTER™ DUAL Industrial Temperature with Fiber Support (FX) and Flexible Port Switching Dual Port 10/100 Mb/s Ethernet Physical Layer Tranceiver Check for Samples: DP83849IF 1 Introduction 1.1 • • • • • • • • • 123 • • • • • Low-Power 3.3V, 0.18µm CMOS Technology Low Power Consumption <600mW Typical 3.
PAGE 2
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 1.3 www.ti.com Description The number of applications requiring Ethernet Connectivity continues to expand. Along with this increased market demand is a change in application requirements. Where single channel Ethernet used to be sufficient, many applications such as wireless remote base stations and industrial networking now require DUAL Port functionality for redundancy or system management.
PAGE 3
DP83849IF www.ti.com 1 2 3 4 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Introduction 4.23 AC Specifications — 10 Mb/s Heartbeat Timing ... 24 1.1 .............................................. 1 ............................................. 1 1.2 Applications .......................................... 1 1.3 Description ........................................... 2 Device Information ...................................... 5 2.1 System Diagram ..................................... 5 2.
PAGE 4
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 9.3 ...................................... ......................................... REGISTER DEFINITION ........................... SOFT RESET 10 Register Block 10.1 4 www.ti.com ............... 69 10.2 EXTENDED REGISTERS - PAGE 0 70 10.3 LINK DIAGNOSTICS REGISTERS - PAGE 2 ...... 93 73 Revision History Contents ............................................
PAGE 5
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 2 Device Information 2.1 System Diagram Magnetics M II/R M II/S N I MAC Magnetics DP838491F MPU/CPU Port A M II/R M II/S N I 25 MHz Clock Source 10BASE-T RJ45 Port B or 100BASE-TX 10BASE-T RJ45 MAC 10BASE-FX or 100BASE-TX Status LEDs 10BASE-FX Typical Application 2.
PAGE 6
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 3 Pin Descriptions The DP83849IF pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial Management Interface • MAC Data Interface • Clock Interface • LED Interface • JTAG Interface • Reset and Power Down • Strap Options • 10/100 Mb/s PMD Interface • Special Connect Pins • Power and Ground Pins NOTE Strapping pin option. Please see Section 3.9 for strap definitions.
PAGE 7
DP83849IF www.ti.com 3.1 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Connection Diagram Figure 3-1.
PAGE 8
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 3.2 PACKAGE PIN ASSIGNMENTS PFC Pin # 8 www.ti.
PAGE 9
DP83849IF www.ti.com 3.3 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 SERIAL MANAGEMENT INTERFACE Signal Name Type Pin # MDC I 67 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. MDIO I/O 66 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY.
PAGE 10
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Signal Name COL_A COL_B 3.5 Type Pin # O 3 59 www.ti.com Description MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes. While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).
PAGE 11
DP83849IF www.ti.com 3.7 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 JTAG INTERFACE Signal Name Type Pin # Description TCK I, PU 72 TDO O 73 TEST OUTPUT TMS I, PU 74 TEST MODE SELECT TRSTN I, PU 75 TEST CLOCK This pin has a weak internal pullup. This pin has a weak internal pullup. TEST RESET Active low test reset. This pin has a weak internal pullup. TDI I, PU 76 TEST DATA INPUT This pin has a weak internal pullup. 3.
PAGE 12
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Signal Name www.ti.com Type Pin # Description FX_EN_A (COL_A) FX_EN_B (COL_B) S, I, PD 3 59 AN_EN (LED_ACT/LED_COL_A) AN1_A (LED_SPEED_A) AN0_A (LED_LINK_A) S, O, PU 21 20 19 FX ENABLE: Default is to disable 100BASE-FX (Fiber) mode. This strapping option enables 100BASE-FX. An external pull-up will enable 100BASE-FX mode. Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability set by AN0 and AN1 pins.
PAGE 13
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 3.10 10 Mb/s AND 100 Mb/s PMD INTERFACE Signal Name Type Pin # TPTDM_A/FXTDM_A TPTDP_A/FXTDP_A TPTDM_B/FXTDM_B TPTDP_B/FXTDP_B I/O 26 27 36 35 10BASE-T or 100BASE-TX or 100BASE-FX Transmit Data In 10BASE-T or 100BASE-TX: Differential common driver transmit output (PMD Output Pair). These differential outputs are automatically configured to either 10BASE-T or 100BASE-TX signaling.
PAGE 14
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 4 Electrical Specifications 4.1 Absolute Maximum Ratings (1) (2) Supply Voltage (VCC) -0.5 V to 4.2 V DC Input Voltage (VIN) -0.5V to VCC + 0.5V DC Output Voltage (VOUT) -0.5V to VCC + 0.5V Maximum Temperature for TA = 85 °C 108 °C Maximum Die Temperature (Tj) 150 °C Storage Temperature (TSTG ) -65°C to 150°C Lead Temp. (TL) (Soldering, 10 sec.) 260 °C ESD Rating (RZAP = 1.5k, CZAP = 100 pF) 4.0 kV (1) (2) 4.
PAGE 15
DP83849IF www.ti.com 4.
PAGE 16
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com AC Specifications — Power Up Timing (1) 4.5 Parameter T2.1.1 T2.1.2 Notes Min Post Power Up Stabilization time prior to MDC preamble for register accesses Description MDIO is pulled high for 32-bit serial management initialization 167 Typ Max Units ms Hardware Configuration Latch-in Time from power up Hardware Configuration Pins are described in the Pin Description section. 167 ms X1 Clock must be stable for a min.
PAGE 17
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 AC Specifications — Reset Timing (1) 4.6 Parameter Description Notes Min Typ Max Units T2.2.1 Post RESET Stabilization time prior to MDC preamble for register accesses MDIO is pulled high for 32-bit serial management initialization 3 µs T2.2.2 Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard) Hardware Configuration Pins are described in the Pin Description section 3 µs T2.2.
PAGE 18
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 4.7 www.ti.com AC Specifications — MII Serial Management Timing Parameter Description Notes Min T2.3.1 MDC to MDIO (Output) Delay Time 0 T2.3.2 MDIO (Input) to MDC Setup Time 10 T2.3.3 MDIO (Input) to MDC Hold Time 10 T2.3.4 MDC Frequency Typ Max Units 30 ns ns ns 2.5 25 MHz MDC T2.3.4 T2.3.1 MDIO (output) MDC T2.3.2 Valid Data MDIO (input) 4.8 T2.3.
PAGE 19
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 4.10 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Latency Timing (1) Parameter T2.6.1 (1) Description Notes TX_CLK to PMD Output Pair Latency Min 100BASE-TX and 100BASE-FX modes Typ Max Units 5 bits For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the PMD Output Pair.
PAGE 20
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 4.12 AC Specifications — 100BASE-TX Transmit Timing (tR/F & Jitter) (1) Parameter T2.8.1 Description 100 Mb/s tR and tF Mismatch T2.8.2 (1) (2) Notes Min Typ Max Units 3 4 5 ns 500 ps 1.
PAGE 21
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 4.14 AC Specifications — 100BASE-TX and 100BASE-FX MII Receive Packet Deassertion Timing (1) Parameter T2.10.1 (1) (2) Description Notes Carrier Sense OFF Delay (2) Min Typ 100BASE-TX mode 24 100BASE-FX mode 14 Max Units bits 1 bit time = 10 ns in 100 Mb/s mode. Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” code group to the deassertion of Carrier Sense.
PAGE 22
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 4.17 AC Specifications — 10 Mb/s Serial Mode Transmit Timing Min Typ Max Units T2.13.1 Parameter TX_CLK High Time Description 10 Mb/s Serial mode Notes 20 25 30 ns T2.13.2 TX_CLK Low Time 10 Mb/s Serial mode 70 75 80 ns T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise 10 Mb/s Serial mode 25 ns T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 10 Mb/s Serial mode 0 ns T2.13.1 T2.13.2 TX_CLK T2.13.3 T2.13.
PAGE 23
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 4.20 AC Specifications — 10BASE-T Transmit Timing (End of Packet) Parameter T2.16.1 Description Notes End of Packet High Time Min Typ 250 300 Max Units ns 250 300 ns (with '0' ending bit) T2.16.2 End of Packet High Time (with '1' ending bit) TX_CLK TX_EN T2.16.1 PMD Output Pair 0 0 T2.16.2 PMD Output Pair 1 1 4.21 AC Specifications — 10BASE-T Receive Timing (Start of Packet) (1) (2) Parameter Description Notes T2.17.
PAGE 24
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 4.22 AC Specifications — 10BASE-T Receive Timing (End of Packet) Parameter T2.18.1 Description Notes Min Typ Carrier Sense Turn Off Delay 1 0 1 Max Units 1 µs IDLE PMD Input Pair RX_CLK T2.18.1 CRS 4.23 AC Specifications — 10 Mb/s Heartbeat Timing Parameter Description Notes Min Typ Max Units T2.19.1 CD Heartbeat Delay 10 Mb/s half-duplex mode 1200 ns T2.19.
PAGE 25
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 4.25 AC Specifications — 10BASE-T Normal Link Pulse Timing (1) Parameter Description Notes Min Typ Max Units T2.21.1 Pulse Width 100 ns T2.21.2 Pulse Period 16 ms (1) These specifications represent transmit timings. T2.21.2 T2.21.1 Normal Link Pulse(s) 4.26 AC Specifications — Auto-Negotiation Fast Link Pulse (FLP) Timing (1) Parameter Description Notes Min Typ Max Units T2.22.1 Clock, Data Pulse Width 100 ns T2.
PAGE 26
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 4.28 AC Specifications — 100 Mb/s Internal Loopback Timing (1) (2) Parameter T2.24.1 (1) (2) Description TX_EN to RX_DV Loopback Notes 100 Mb/s internal loopback mode Min Typ Max Units 240 ns Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
PAGE 27
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 4.29 AC Specifications — 10 Mb/s Internal Loopback Timing (1) Parameter T2.25.1 (1) Description TX_EN to RX_DV Loopback Notes Min Typ 10 Mb/s internal loopback mode Max Units 2 µs Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN. TX_CLK TX_EN TXD[3:0] CRS T2.25.1 RX_CLK RX-DV RXD[3:0] 4.30 AC Specifications — RMII Transmit Timing Parameter Description Notes T2.26.1 X1 Clock Period T2.26.
PAGE 28
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 4.31 AC Specifications — RMII Receive Timing (1) (2) (3) (4) Parameter Description Notes T2.27.1 X1 Clock Period T2.27.2 RXD[1:0], CRS_DV, RX_DV and RX_ER output delay from X1 rising T2.27.3 CRS ON delay (100Mb) (5) T2.27.4 CRS OFF delay (100Mb) T2.27.5 (1) (2) (3) (4) (5) Min Typ 50 MHz Reference Clock 2 18.
PAGE 29
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 4.32 AC Specifications — Single Clock MII (SCMII) Transmit Timing (1) Parameter Description Notes Min T2.28.1 X1 Clock Period 25 MHz Reference Clock T2.28.2 TXD[3:0], TX_EN Data Setup To X1 rising 4 T2.28.3 TXD[3:0], TX_EN Data Hold From X1 rising 2 T2.28.
PAGE 30
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 4.34 AC Specifications — Isolation Timing Parameter T2.30.1 Description Notes Min Typ From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode Max Units 100 µs Clear Bit 10 of BMCR (return to normal operation from isolate mode) T2.30.1 MODE ISOLATE NORMAL 4.35 AC Specifications — CLK2MAC Timing (1) Parameter T2.31.1 T2.31.
PAGE 31
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 5 Configuration This section includes information on the various configuration options available with the DP83849IF. The configuration options described below include: • Media Configuration • Auto-Negotiation • PHY Address and LEDs • Half Duplex vs. Full Duplex • Isolate mode • Loopback mode • BIST 5.1 MEDIA CONFIGURATION The DP83849IF supports both Twister Pair (100BASE-TX and 10BASE-T) and Fiber (100BASE-FX) media.
PAGE 32
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 5-1. Auto-Negotiation Modes AN_EN AN1 AN0 0 0 0 10BASE-T, Half-Duplex Forced Mode 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 100BASE-TX, Full-Duplex 0 1 1 AN_EN AN1 AN0 1 0 0 10BASE-T, Half/Full-Duplex 1 0 1 100BASE-TX, Half/Full-Duplex 1 1 0 10BASE-T Half-Duplex Advertised Mode 100BASE-TX, Half-Duplex 1 1 1 10BASE-T, Half/Full-Duplex 100BASE-TX, Half/Full-Duplex 5.2.
PAGE 33
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 The Auto-Negotiation Expansion Register (ANER) indicates additional Auto-Negotiation status.
PAGE 34
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 5.3 www.ti.com AUTO-MDIX When enabled, this function utilizes Auto-Negotiation to determine the proper configuration for transmission and reception of data and subsequently selects the appropriate MDI pair for MDI/MDIX operation. The function uses a random seed to control switching of the crossover circuitry. This implementation complies with the corresponding IEEE 802.3 Auto-Negotiation and Crossover Specifications.
PAGE 35
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 PHYAD4 = 0 PHYAD3 = 0 RXD1_A RXD1_A RXD1_B RXD0_B The DP83849IF can Auto-Negotiate or parallel detect to a specific technology depending on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the DP83849IF is in Isolate mode. PHYAD2 = 0 PHYAD1 = 1 2.2 k: VCC Figure 5-1. PHYAD Strapping Example 5.
PAGE 36
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com Activity is defined as configured in LEDACT_RX, bit 8 of register LEDCR (18h). If LEDACT_RX is 0, Activity is signaled for either transmit or receive. If LEDACT_RX is 1, Activity is only signaled for receive. The LED_SPEED pin indicates 10 or 100 Mb/s data rate of the port. The LED is ON when operating in 100Mb/s mode and OFF when operating in 10Mb/s mode. The functionality of this LED is independent of mode selected.
PAGE 37
DP83849IF www.ti.com 5.5.2 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 LED Direct Control The DP83849IF provides another option to directly control any or all LED outputs through the LED Direct Control Register (LEDCR), address 18h. The register does not provide read access to LEDs. 5.6 HALF DUPLEX vs. FULL DUPLEX The DP83849IF supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds. Half-duplex relies on the CSMA/CD protocol to handle collisions and network access.
PAGE 38
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com The pass/fail status of the BIST is stored in the BIST status bit in the PHYCR register. The status bit defaults to 0 (BIST fail) and will transition on a successful comparison. If an error (mis-compare) occurs, the status bit is latched and is cleared upon a subsequent write to the Start/Stop bit.
PAGE 39
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 6 MAC Interface The DP83849IF supports several modes of operation using the MII interface pins. The options are defined in the following sections and include: • MII Mode • RMII Mode • 10 Mb Serial Network Interface (SNI) • Single Clock MII Mode (SCMII) In addition, the DP83849IF supports the standard 802.3u MII Serial Management Interface and a Flexible MII Port Assignment scheme.
PAGE 40
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. 6.1.
PAGE 41
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 The elasticity buffer will force Frame Check Sequence errors for packets which overrun or underrun the FIFO. Underrun and Overrun conditions can be reported in the RMII and Bypass Register (RBR). The following table indicates how to program the elasticity buffer fifo (in 4-bit increments) based on expected max packet size and clock accuracy. It assumes both clocks (RMII Reference clock and far-end Transmitter clock) have the same accuracy.
PAGE 42
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 6-2. Supported SCMII Packet Sizes at +/-50ppm Frequency Accuracy Start Threshold RBR[1:0] 6.
PAGE 43
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Table 6-3. RX MII Port Mapping Controls RBR[12:11] Desired RX Channel Destination 00 Normal Port 01 Opposite Port 10 Both Ports 11 Disabled Table 6-4.
PAGE 44
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 6.5.3 www.ti.com Common Flexible MII Port Configurations Table 6-7.
PAGE 45
DP83849IF www.ti.com • • • • • • • • • 6.6 6.6.1 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 RMII Mode: Both Channels must have RMII Mode enabled or disabled concurrently due to the internal reference clocking scheme. In Full Port Swap Mode, Channels are not required to have a common speed. 10Base-T Serial Mode: This MAC-side mode, also known as Serial Network Interface (SNI), may not be used when both channels share data connections (Extender/Media Converter or Broadcast TX MII Port).
PAGE 46
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com In addition, the MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high. In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous logic ones on MDIO to provide the DP83849IF with a sequence that can be used to establish synchronization.
PAGE 47
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 The DP83849IF requires a single initialization sequence of 32 bits of preamble following hardware/software reset. This requirement is generally met by the mandatory pull-up resistor on MDIO in conjunction with a continuous MDC, or the management access made to determine whether Preamble Suppression is supported.
PAGE 48
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 7 Architecture This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following: • 100BASE-TX Transmitter • 100BASE-TX Receiver • 100BASE-FX Operation • 10BASE-T Transceiver Module 7.
PAGE 49
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Table 7-1.
PAGE 50
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 7.1.2 www.ti.com Scrambler The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels at the PMD and on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (i.e.
PAGE 51
DP83849IF www.ti.com 7.2.1 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Analog Front End In addition to the Digital Equalization and Gain Control, the DP83849IF includes Analog Equalization and Gain Control in the Analog Front End. The Analog Equalization reduces the amount of Digital Equalization required in the DSP. 7.2.2 Digital Signal Processor The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander Compensation.
PAGE 52
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 7.2.2.1 www.ti.com Digital Adaptive Equalization and Gain Control When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the frequency content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the scrambled data stream.
PAGE 53
DP83849IF www.ti.com 7.2.2.2 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Base Line Wander Compensation Figure 7-4. 100BASE-TX BLW Event The DP83849IF is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer” pattern. BLW can generally be defined as the change in the average DC content, relatively short period over time, of an AC coupled digital transmission over a given transmission medium. (i.e.
PAGE 54
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 7.2.7 www.ti.com Descrambler A serial descrambler is used to de-scramble the received NRZ data.
PAGE 55
DP83849IF www.ti.com 7.3 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 100BASE-FX OPERATION The DP83849IF provides IEEE 802.3 compliant 100BASE-FX operation. Configuration of FX mode is via strap option, or through the register interface. 7.3.1 100BASE-FX Transmit In 100BASE-FX mode, the device Transmit Pins connect to an industry standard Fiber Transceiver with PECL signalling through a capacitively coupled circuit. In FX mode, the device bypasses the Scrambler and the MLT3 encoder.
PAGE 56
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 7.4.1.2 www.ti.com Full Duplex Mode In Full Duplex mode the DP83849IF is capable of simultaneously transmitting and receiving without asserting the collision signal. The DP83849IF's 10 Mb/s ENDEC is designed to encode and decode simultaneously. 7.4.2 Smart Squelch The smart squelch is responsible for determining when valid data is present on the differential receive inputs.
PAGE 57
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 When heartbeat is enabled, approximately 1 µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10-bit times is generated to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. The SQE test is inhibited when the PHY is set in full duplex mode. SQE can also be inhibited by setting the HEARTBEAT_DIS bit in the 10BTSCR register. 7.4.
PAGE 58
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 7.4.9 www.ti.com Transmitter The encoder begins operation when the Transmit Enable input (TX_EN) goes high and converts NRZ data to pre-emphasized Manchester data for the transceiver. For the duration of TX_EN, the serialized Transmit Data (TXD) is encoded for the transmit-driver pair (PMD Output Pair). TXD must be valid on the rising edge of Transmit Clock (TX_CLK). Transmission ends when TX_EN deasserts.
PAGE 59
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 8 Design Guidelines 8.1 TPI NETWORK CIRCUIT Figure 8-1 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. Below is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application.
PAGE 60
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 8.2 www.ti.com FIBER NETWORK CIRCUIT Figure 8-2 shows the recommended circuit for a 100 Mb/s fiber pair interface. Vdd 50: 50: 130: 130: 130: 130: 130: 0.1 PF FXTDP TD+ FXTDM TD- FXSD SD FXRDP RD+ FXRDM RD- 80: 80: 80: 80: Fiber Transceiver 0.1 PF 80: PLACE RESISTORS CLOSE TO THE FIBER TRANSCEIVER PLACE RESISTORS AND CAPACITORS CLOSE TO THE DEVICE All values are typical abd are +/- 1% Figure 8-2.
PAGE 61
DP83849IF www.ti.com 8.4 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 CLOCK IN (X1) REQUIREMENTS The DP83849IF supports an external CMOS level oscillator source or a crystal resonator device. Oscillator If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating. Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 8-1 and Table 8-2.
PAGE 62
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 8-1. 25 MHz Oscillator Specification Parameter Min Typ Frequency Units Condition MHz Frequency Tolerance ±50 ppm Operational Temperature Frequency Stability ±50 ppm 1 year aging Rise / Fall Time 6 nsec 20% - 80% Jitter 800 (1) psec Short term Jitter 800 (1) psec Long term Symmetry (1) Max 25 40% 60% Duty Cycle This limit is provided as a guide for component selection and not ensured by production testing.
PAGE 63
DP83849IF www.ti.com 8.5 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 POWER FEEDBACK CIRCUIT To ensure correct operation for the DP83849IF, parallel caps with values of 10 µF and 0.1 µF should be placed close to pin 31 (PFBOUT) of the device. Pin 7 (PFBIN1), pin 28 (PFBIN2), pin 34 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (.1 µF). See Figure 8-4 below for proper connections. Pin 31 (PFBOUT) 10 PF Pin 7 (PFBIN1) 0.1 PF 0.
PAGE 64
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com Example: To generate an interrupt on a change of link status or on a change of energy detect power state, the steps would be: • Write 0003h to MICR to set INTEN and INT_OE • Write 0060h to MISR to set ED_INT_EN and LINK_INT_EN • Monitor PWRDOWN_INT pin When PWRDOWN_INT pin asserts low, the user would read the MISR register to see if the ED_INT or LINK_INT bits are set, i.e. which source caused the interrupt.
PAGE 65
DP83849IF www.ti.com 8.8.1.3 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 100MB Cable Length Estimation The DP83849IF provides a method of estimating cable length based on electrical characteristics of the 100Mb Link. This essentially provides an effective cable length rather than a measurement of the physical cable length. The cable length estimation is only available in 100Mb mode of operation with a valid Link status.
PAGE 66
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com To allow the Link Quality Monitor to interrupt the system, the Interrupt must be enabled through the interrupt control registers, MICR (11h) and MISR (12h). 8.8.2.2 Checking Current Parameter Values Prior to setting Threshold values, it is recommended that software check current adapted values. The thresholds may then be set relative to the adapted values.
PAGE 67
DP83849IF www.ti.com 8.8.4 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 TDR Pulse Generator The TDR implementation can send two types of TDR pulses. The first option is to send 50ns or 100ns link pulses from the 10Mb Common Driver. The second option is to send pulses from the 100Mb Common Driver in 8ns increments up to 56ns in width. The 100Mb pulses will alternate between positive and negative pulses.
PAGE 68
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 8.8.7 www.ti.com TDR Results The TDR function monitors data from the Analog to Digital Converter (ADC) to detect both peak values and values above a programmable threshold. It can be programmed to detect maximum or minimum values. In addition, it records the time, in 8ns intervals, at which the peak or threshold value first occurs.
PAGE 69
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 9 Reset Operation The DP83849IF includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal operation, the device can be reset by a hardware or software reset. 9.1 HARDWARE RESET A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 ms, to the RESET_N pin.
PAGE 70
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 10 Register Block Table 10-1.
PAGE 71
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Table 10-2.
PAGE 72
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 10-2.
PAGE 73
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.
PAGE 74
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.1.1 www.ti.com Basic Mode Control Register (BMCR) Table 10-3.
PAGE 75
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.1.2 Basic Mode Status Register (BMSR) Table 10-4.
PAGE 76
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83849IF. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision number. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. TI's IEEE assigned OUI is 080017h. 10.1.
PAGE 77
DP83849IF www.ti.com 10.1.5 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation. Any writes to this register prior to completion of Auto-Negotiation (as indicated in the Basic Mode Status Register (address 01h) Auto-Negotiation Complete bit, BMSR[5]) should be followed by a renegotiation.
PAGE 78
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.1.6 www.ti.com Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page) This register contains the advertised abilities of the Link Partner as received during Auto-Negotiation. The content changes after the successful auto-negotiation if Next-pages are supported. Table 10-8.
PAGE 79
DP83849IF www.ti.com 10.1.7 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page) Table 10-9. Auto-Negotiation Link Partner Ability Register (ANLPAR) (Next Page), address 05h Bit 15 Bit Name NP Default 0, RO 14 ACK 0, RO 13 MP 0, RO 12 ACK2 0, RO 11 TOGGLE 0, RO 10:0 CODE <000 0000 0000>, RO 10.1.8 Description Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer.
PAGE 80
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.1.9 www.ti.com Auto-Negotiation Next Page Transmit Register (ANNPTR) This register contains the next page information sent by this device to its Link Partner during AutoNegotiation. Table 10-11. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 07h Bit 15 Bit Name NP 14 13 RESERVED MP 12 ACK2 11 TOG_TX 10:0 CODE 80 Default 0, RW Description Next Page Indication: 0 = No other Next Page Transfer desired.
PAGE 81
DP83849IF www.ti.com 10.1.10 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 PHY Status Register (PHYSTS) This register provides a single location within the register set for quick access to commonly accessed information. Table 10-12.
PAGE 82
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com Table 10-12. PHY Status Register (PHYSTS), address 10h (continued) Bit 5 Bit Name JABBER DETECT Default 0, RO 4 AUTO-NEG COMPLETE 0, RO 3 LOOPBACK STATUS 0, RO 2 DUPLEX STATUS 0, RO 1 SPEED STATUS 0, RO 0 LINK STATUS 0, RO (1) Description Jabber Detect: This bit only has meaning in 10 Mb/s mode.
PAGE 83
DP83849IF www.ti.com 10.1.12 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 MII Interrupt Status and Misc. Control Register (MISR) This register contains event status and enables for the interrupt function. If an event has occurred since the last read of this register, the corresponding status bit will be set. If the corresponding enable bit in the register is set, an interrupt will be generated if the event occurs. The MICR register controls must also be set to allow interrupts.
PAGE 84
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.1.13 www.ti.com Page Select Register (PAGESEL) This register is used to enable access to the Link Diagnostics Registers. Table 10-15. Page Select Register (PAGESEL), address 13h Bit 15:2 1:0 Bit Name RESERVED PAGE_SEL Default 0, RO 0, RW Description RESERVED: Writes ignored, read as 0 Page_Sel Bit: Selects between paged registers for address 14h to 1Fh. 0 = Extended Registers Page 0 1 = RESERVED 2 = Link Diagnostics Registers Page 2 10.
PAGE 85
DP83849IF www.ti.com 10.2.3 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 100 Mb/s PCS Configuration and Status Register (PCSR) This register contains control and status information for the 100BASE Physical Coding Sublayer. Table 10-18.
PAGE 86
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.2.4 www.ti.com RMII and Bypass Register (RBR) This register configures the RMII/MII Interface Mode of operation. This register controls selecting MII, RMII, or Single Clock MII mode for Receive or Transmit. In addition, several additional bits are included to allow datapath selection for Transmit and Receive in multiport applications. Table 10-19.
PAGE 87
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Table 10-19. RMII and Bypass Register (RBR), addresses 17h (continued) Bit 4 Bit Name RMII_REV1_0 Default 0, RW 3 RX_OVF_STS 0, RO/COR 2 RX_UNF_STS 0, RO/COR 1:0 ELAST_BUF[1:0] 01, RW 10.2.5 Description Reduced MII Revision 1.0: 0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet to indicate deassertion of CRS. 1 = (RMII revision 1.0) CRS_DV will remain asserted until final data is transferred.
PAGE 88
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.2.6 www.ti.com PHY Control Register (PHYCR) This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause Negotiation status. Table 10-21.
PAGE 89
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Table 10-21. PHY Control Register (PHYCR), address 19h (continued) Bit 7 Bit Name BP_STRETCH Default 0, RW 6 5 LED_CNFG[1] LED_CNFG[0] 0, RW Strap, RW Description Bypass LED Stretching: This will bypass the LED stretching and the LEDs will reflect the internal value. 1 = Bypass LED stretching. 0 = Normal operation.
PAGE 90
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.2.7 www.ti.com 10 Base-T Status/Control Register (10BTSCR) This register is used for control and status for 10BASE-T device operation. Table 10-22.
PAGE 91
DP83849IF www.ti.com 10.2.8 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 CD Test and BIST Extensions Register (CDCTRL1) This register controls test modes for the 10BASE-T Common Driver. In addition it contains extended control and status for the packet BIST function. Table 10-23.
PAGE 92
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.2.10 www.ti.com Energy Detect Control (EDCR) This register provides control and status for the Energy Detect function. Table 10-25.
PAGE 93
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.3 LINK DIAGNOSTICS REGISTERS - PAGE 2 Page 2 Link Diagnostics Registers are accessible by setting bits [1:0] = 10 of PAGESEL (13h). 10.3.1 100Mb Length Detect Register (LEN100_DET), Page 2, address 14h This register contains linked cable length estimation in 100Mb operation. The cable length is an estimation of the effective cable length based on the characteristics of the recovered signal.
PAGE 94
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.3.3 www.ti.com TDR Control Register (TDR_CTRL), Page 2, address 16h This register contains control for the Time Domain Reflectometry (TDR) cable diagnostics. The TDR cable diagnostics sends pulses down the cable and captures reflection data to be used to estimate cable length and detect certain cabling faults. Table 10-28.
PAGE 95
DP83849IF www.ti.com 10.3.4 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 TDR Window Register (TDR_WIN), Page 2, address 17h This register contains sample window control for the Time Domain Reflectometry (TDR) cable diagnostics. The two values contained in this register specify the beginning and end times for the window to monitor the response to the transmitted pulse. Time values are in 8ns increments.
PAGE 96
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 10.3.7 www.ti.com Variance Control Register (VAR_CTRL), Page 2, address 1Ah The Variance Control and Data Registers provide control and status for the Cable Signal Quality Estimation function. The Cable Signal Quality Estimation allows a simple method of determining an approximate Signal-to-Noise Ratio for the 100Mb receiver.
PAGE 97
DP83849IF www.ti.com 10.3.9 SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Link Quality Monitor Register (LQMR), Page 2, address 1Dh This register contains the controls for the Link Quality Monitor function. The Link Quality Monitor provides a mechanism for programming a set of thresholds for DSP parameters. If the thresholds are violated, an interrupt will be asserted if enabled in the MISR.
PAGE 98
DP83849IF SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 www.ti.com 10.3.10 Link Quality Data Register (LQDR), Page 2 This register provides read/write control of thresholds for the 100Mb Link Quality Monitor function. The register also provides a mechanism for reading current adapted parameter values. Threshold values may not be written if the device is powered-down. Table 10-35.
PAGE 99
DP83849IF www.ti.com SNOSAX8D – JUNE 2009 – REVISED APRIL 2013 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April 2013) to Revision D • Changed layout of National Data Sheet to TI format Page ..........................................................................
PAGE 100
PACKAGE OPTION ADDENDUM www.ti.
PAGE 101
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device DP83849IFVSX/NOPB Package Package Pins Type Drawing TQFP PFC 80 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 15.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.0 1.45 20.0 24.
PAGE 102
PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DP83849IFVSX/NOPB TQFP PFC 80 1000 367.0 367.0 45.
PAGE 103
MECHANICAL DATA MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996 PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 60 0,08 M 41 61 40 80 21 1 0,13 NOM 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 0,25 14,20 SQ 13,80 0,05 MIN 0°– 7° 0,75 0,45 1,05 0,95 Seating Plane 0,08 1,20 MAX 4073177 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
PAGE 104
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.