Datasheet

October 2006

Tung Ngo

v1.1

National Semiconductor Corp 6

Demo II Block Diagram

PCB Physical Layout

• FR4 material

• Trace impedance Differential impedance 100 ohms, +/- 5%

• Uniform supply & ground plane

• 5.875” (height) 5.25” (length)

• 4 layers

• Combination of through-hole and surface mount technology

Demo II Interface requirements

• System interface will be via the MII connector, or MII/MRII/SNI header

• RJ-45 for network connection

• JTAG access via 2x5 header

• On Board Serial Management Circuit

Demo II Performance

The DP83849 Demo II supports line speed Ethernet network communications.

Signal quality, which affects IEEE compliance, can vary depending on board layout, power supplies, and

components used, esp. isolation magnetics.

This reference design was NOT designed for operation over extreme temperature ranges.

25MHz

Xtal

LED

PHYAD

Strap

JTAG

DP83849

Dual

PHYTER

MII/RMII/SNI

MAGNETIC MAGNETIC

RJ-45

POE connector

Transceiver

LED

Integrity

Interface

MII/RMII/SNI

Reset