Datasheet

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DP83849ID
8 SD_OPTION 1, RW Signal Detect Option:
1 = Default operation. Link will be asserted following detection of
valid signal level and Descrambler Lock. Link will be maintained as
long as signal level is valid. A loss of Descrambler Lock will not
cause Link Status to drop.
0 = Modified signal detect algorithm. Link will be asserted following
detection of valid signal level and Descrambler Lock. Link will be
maintained as long as signal level is valid and Descrambler re
-
mains locked.
7 DESC_TIME 0, RW Descrambler Timeout:
Increase the descrambler timeout. When set this should allow the
device to receive larger packets (>9k bytes) without loss of syn-
chronization.
1 = 2ms
0 = 722us (per ANSI X3.263: 1995 (TP-PMD) 7.2.3.3e)
6 FX_EN Strap, RW FX Fiber Mode Enable:
This bit is set when the FX_EN strap option is selected (pulled high)
for the respective port.
1 = Enables FX operation
0 = Disables FX operation
5 FORCE_100_OK 0, RW Force 100Mb/s Good Link:
1 = Forces 100Mb/s Good Link.
0 = Normal 100Mb/s operation.
4 RESERVED 0, RO RESERVED: Writes ignored, Read as 0
3 FEFI_EN Strap, RW Far End Fault Indication Mode Enable:
This bit is set when the FX_EN strap option is selected for the re-
spective port.
1 = FEFI Mode Enabled
0 = FEFI Mode Disabled
2 NRZI_BYPASS 0, RW NRZI Bypass Enable:
1 = NRZI Bypass Enabled.
0 = NRZI Bypass Disabled.
1 SCRAM
BYPASS
Strap, RW Scrambler Bypass Enable:
This bit is set when the FX_EN strap option is selected for the re-
spective port. In the FX mode, the scrambler is bypassed.
1 = Scrambler Bypass Enabled
0 = Scrambler Bypass Disabled
0 DESCRAM
BYPASS
Strap, RW Descrambler Bypass Enable:
This bit is set when the FX_EN strap option is selected for the re-
spective port. In the FX mode, the descrambler is bypassed.
1 = Descrambler Bypass Enabled
0 = Descrambler Bypass Disabled
Table 35. 100 Mb/s PCS Configuration and Status Register (PCSR), address 16h (Continued)
Bit Bit Name Default Description