Datasheet

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DP83849C
1.5 Reset and Power Down
1.6 Strap Options
The DP83849C uses many of the functional pins as strap
options. The values of these pins are sampled during reset
and used to strap the device into specific modes of opera
-
tion. The strap option pin assignments are defined below.
The functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pull-down or pull-up to
change the default strap option. If the default option is
required, then there is no need for external pull-up or pull
down resistors. Since these pins may have alternate func
-
tions after reset is deasserted, they should not be con-
nected directly to VCC or GND.
Signal Name Type Pin # Description
RESET_N I, PU 71 RESET: Active Low input that initializes or re-initializes the
DP83849C. Asserting this pin low for at least 1 µs will force a reset
process to occur. All internal registers will re-initialize to their de
-
fault states as specified for each bit in the Register Block section.
All strap options are re-initialized as well.
PWRDOWN_INT_A
PWRDOWN_INT_B
I, PU 18
44
The default function of this pin is POWER DOWN.
POWER DOWN: The pin is an active low input in this mode and
should be asserted low to put the device in a Power Down mode.
INTERRUPT: The pin is an open drain output in this mode and will
be asserted low when an interrupt condition occurs. Although the
pin has a weak internal pull-up, some applications may require an
external pull-up resister. Register access is required for the pin to
be used as an interrupt mechanism. See
Section 5.5.2 Interrupt
Mechanism for more details on the interrupt mechanisms.
Signal Name Type Pin # Description
PHYAD1 (RXD0_A)
PHYAD2 (RXD1_A)
PHYAD3 (RXD0_B)
PHYAD4 (RXD1_B)
S, O, PD
S, O, PD
S, O, PD
S, O, PD
4
5
58
57
PHY ADDRESS [4:1]: The DP83849C provides four PHY ad-
dress pins, the state of which are latched into the PHYCTRL reg-
ister at system Hardware-Reset. Phy Address[0] selects between
ports A and B.
The DP83849C supports PHY Address strapping for Port A even
values 0 (<0000_0>) through 30 (<1111_0>). Port B will be
strapped to odd values 1 (<0000_1>) through 31 (<1111_1>).
PHYAD[4:1] pins have weak internal pull-down resistors.