Datasheet

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DP83848YB
7.2.7 RMII and Bypass Register (RBR)
This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.
7.2.8 LED Direct Control Register (LEDCR)
This register provides the ability to directly control any or all LED outputs. It does not provide read access to LEDs.
Table 27. RMII and Bypass Register (RBR), addresses 0x17
Bit Bit Name Default Description
15:6 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
5 RMII_MODE Strap, RW Reduced MII Mode:
0 = Standard MII Mode
1 = Reduced MII Mode
4 RMII_REV1_0 0, RW Reduce MII Revision 1.0:
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet
to indicate deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data
is transferred. CRS_DV will not toggle at the end of a packet.
3 RX_OVF_STS 0, RO RX FIFO Over Flow Status:
0 = Normal
1 = Overflow detected
2 RX_UNF_STS 0, RO RX FIFO Under Flow Status:
0 = Normal
1 = Underflow detected
1:0 ELAST_BUF[1:0] 01, RW Receive Elasticity Buffer. This field controls the Receive Elastic-
ity Buffer which allows for frequency variation tolerance between
the 50MHz RMII clock and the recovered data. The following val
-
ues indicate the tolerance in bits for a single packet. The minimum
setting allows for standard Ethernet frame sizes at +/-50ppm accu-
racy for both RMII and Receive clocks. For greater frequency tol-
erance the packet lengths may be scaled (i.e. for +/-100ppm, the
packet lengths need to be divided by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2 bit tolerance (up to 2400 byte packets)
10 = 6 bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)
Table 28. LED Direct Control Register (LEDCR), address 0x18
Bit Bit Name Default Description
15:6 RESERVED 0, RO RESERVED: Writes ignored, read as 0.
5 DRV_SPDLED 0, RW 1 = Drive value of SPDLED bit onto LED_SPD output
0 = Normal operation
4 DRV_LNKLED 0, RW 1 = Drive value of LNKLED bit onto LED_LNK output
0 = Normal operation
3 DRV_ACTLED 0, RW 1 = Drive value of ACTLED bit onto LED_ACT/COL output
0 = Normal operation
2 SPDLED 0, RW Value to force on LED_SPD output
1 LNKLED 0, RW Value to force on LED_LNK output
0 ACTLED 0, RW Value to force on LED_ACT/COL output