Datasheet

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DP83848YB
7 Collision Test 0, RW Collision Test:
1 = Collision test enabled.
0 = Normal operation.
When set, this bit will cause the COL signal to be asserted in response
to the assertion of TX_EN within 512-bit times. The COL signal will be
de-asserted within 4-bit times in response to the de-assertion of
TX_EN.
6:0 RESERVED 0, RO RESERVED: Write ignored, read as 0.
Table 12. Basic Mode Control Register (BMCR), address 0x00 (Continued)
Bit Bit Name Default Description