Datasheet

DP83848VYB
SNLS266D –MAY 2007–REVISED APRIL 2013 www.ti.com
3.3 SERIAL MANAGEMENT INTERFACE
Signal Name Type Pin # Description
MDC I 31 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output
serial interface which may be asynchronous to transmit and receive clocks. The maximum clock
rate is 25 MHz with no minimum clock rate.
MDIO I/O 30 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be
sourced by the station management entity or the PHY. This pin requires a 1.5 kΩ pullup resistor.
3.4 MAC DATA INTERFACE
Signal Name Type Pin # Description
TX_CLK O 1 MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100 Mb/s mode or 2.5 MHz in 10 Mb/s
mode derived from the 25 MHz reference clock.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for
both transmit and receive.
SNI TRANSMIT CLOCK: 10 MHz Transmit clock output in 10 Mb SNI mode. The MAC should
source TX_EN and TXD_0 using this clock.
TX_EN I, PD 2 MII TRANSMIT ENABLE: Active high input indicates the presence of valid data inputs on
TXD[3:0].
RMII TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD[1:0].
SNI TRANSMIT ENABLE: Active high input indicates the presence of valid data on TXD_0.
TXD_0 I 3 MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0], that accept data synchronous to
TXD_1 4 the TX_CLK (2.5 MHz in 10 Mb/s mode or 25 MHz in 100 Mb/s mode).
TXD_2 5 RMII TRANSMIT DATA: Transmit data RMII input pins, TXD[1:0], that accept data synchronous to
TXD_3 S, I, PD 6 the 50 MHz reference clock.
SNI TRANSMIT DATA: Transmit data SNI input pin, TXD_0, that accept data synchronous to the
TX_CLK (10 MHz in 10 Mb/s SNI mode).
RX_CLK O 38 MII RECEIVE CLOCK: Provides the 25 MHz recovered receive clocks for 100 Mb/s mode and 2.5
MHz for 10 Mb/s mode.
Unused in RMII mode. The device uses the X1 reference clock input as the 50 MHz reference for
both transmit and receive.
SNI RECEIVE CLOCK: Provides the 10 MHz recovered receive clocks for 10 Mb/s SNI mode.
RX_DV S, O, PD 39 MII RECEIVE DATA VALID: Asserted high to indicate that valid data is present on the
corresponding RXD[3:0]. Mll mode by default with internal pulldown.
RMII Synchronous RECEIVE DATA VALID:This signal provide the RMII Receive Data Valid
indication independent of Carrier Sense.
This pin is not used in SNI mode.
RX_ER S, O, PU 41 MII RECEIVE ERROR: Asserted high synchronously to RX_CLK to indicate that an invalid symbol
has been detected within a received packet in 100 Mb/s mode.
RMII RECEIVE ERROR: Asserted high synchronously to X1 whenever an invalid symbol is
detected, and CRS_DV is asserted in 100 Mb/s mode.
This pin is not required to be used by a MAC in either MII or RMII mode, since the Phy is required
to corrupt data on a receive error.
This pin is not used in SNI mode.
RXD_0 S, O, PD 43 MII RECEIVE DATA: Nibble wide receive data signals driven synchronously to the RX_CLK, 25
RXD_1 44 MHz for 100 Mb/s mode, 2.5 MHz for 10 Mb/s mode). RXD[3:0] signals contain valid data when
RXD_2 45 RX_DV is asserted.
RXD_3 46 RMII RECEIVE DATA: 2-bits receive data signals, RXD[1:0], driven synchronously to the X1 clock,
50 MHz.
SNI RECEIVE DATA: Receive data signal, RXD_0, driven synchronously to the RX_CLK. RXD_0
contains valid data when CRS is asserted. RXD[3:1] are not used in this mode.
CRS/CRS_D S, O, PU 40 MII CARRIER SENSE: Asserted high to indicate the receive medium is non-idle.
V RMII CARRIER SENSE/RECEIVE DATA VALID: This signal combines the RMII Carrier and
Receive Data Valid indications. For a detailed description of this signal, see the RMII Specification.
SNI CARRIER SENSE: Asserted high to indicate the receive medium is non-idle. It is used to
frame valid receive data on the RXD_0 signal.
8 Pin Descriptions Copyright © 2007–2013, Texas Instruments Incorporated
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