Datasheet

DP83848VYB

SNLS266D –MAY 2007–REVISED APRIL 2013

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9 Design Guidelines

9.1 TPI NETWORK CIRCUIT

Figure 9-1 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. To the right is a partial

list of recommended transformers. It is important that the user realize that variations with PCB and

component characteristics requires that the application be tested to ensure that the circuit meets the

requirements of the intended application.

Pulse H1102

Pulse H2019

Pulse J0011D21

Pulse J0011D21B

Figure 9-1. 10/100 Mb/s Twisted Pair Interface

9.2 ESD PROTECTION

Typically, ESD precautions are predominantly in effect when handling the devices or board before being

installed in a system. In those cases, strict handling procedures need be implemented during the

manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is

assembled, internal components are less sensitive from ESD events.

See section AC and DC Specifications for ESD rating.

9.3 CLOCK IN (X1) REQUIREMENTS

The DP83848VYB supports an external CMOS level oscillator source or a crystal resonator device.

Oscillator

If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating.

Specifications for CMOS oscillators: 25 MHz in MII Mode and 50 MHz in RMII Mode are listed in Table 9-1

and Table 9-2.

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