Datasheet

DP83848VYB

SNLS266D –MAY 2007–REVISED APRIL 2013

www.ti.com

7.3 10BASE-T TRANSCEIVER MODULE

The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision,

heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not

required on the 10BASE-T interface since this is integrated inside the DP83848VYB. This section focuses

on the general 10BASE-T system level operation.

7.3.1 Operational Modes

The DP83848VYB has two basic 10BASE-T operational modes:

— Half Duplex mode

— Full Duplex mode

Half Duplex Mode

In Half Duplex mode the DP83848VYB functions as a standard IEEE 802.3 10BASE-T transceiver

supporting the CSMA/CD protocol.

Full Duplex Mode

In Full Duplex mode the DP83848VYB is capable of simultaneously transmitting and receiving without

asserting the collision signal. The DP83848VYB's 10 Mb/s ENDEC is designed to encode and decode

simultaneously.

7.3.2 Smart Squelch

The smart squelch is responsible for determining when valid data is present on the differential receive

inputs. The DP83848VYB implements an intelligent receive squelch to ensure that impulse noise on the

receive inputs will not be mistaken for a valid signal. Smart squelch operation is independent of the

10BASE-T operational mode.

The squelch circuitry employs a combination of amplitude and timing measurements (as specified in the

IEEE 802.3 10BSE-T standard) to determine the validity of data on the twisted pair inputs (refer to

Figure 7-5).

The signal at the start of a packet is checked by the smart squelch and any pulses not exceeding the

squelch level (either positive or negative, depending upon polarity) will be rejected. Once this first squelch

level is overcome correctly, the opposite squelch level must then be exceeded within 150 ns. Finally the

signal must again exceed the original squelch level within 150 ns to ensure that the input waveform will

not be rejected. This checking procedure results in the loss of typically three preamble bits at the

beginning of each packet.

Only after all these conditions have been satisfied will a control signal be generated to indicate to the

remainder of the circuitry that valid data is present. At this time, the smart squelch circuitry is reset.

Valid data is considered to be present until the squelch level has not been generated for a time longer

than 150 ns, indicating the End of Packet. Once good data has been detected, the squelch levels are

reduced to minimize the effect of noise causing premature End of Packet detection.

Submit Documentation Feedback

Product Folder Links: DP83848VYB