Datasheet

DP83848VYB

SNLS266D –MAY 2007–REVISED APRIL 2013

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7.2.2.2 Base Line Wander Compensation

Figure 7-4. 100BASE-TX BLW Event

The DP83848VYB is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW)

compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer”

pattern.

BLW can generally be defined as the change in the average DC content, relatively short period over time,

of an AC coupled digital transmission over a given transmission medium. (i.e., copper wire).

BLW results from the interaction between the low frequency components of a transmitted bit stream and

the frequency response of the AC coupling component(s) within the transmission system. If the low

frequency content of the digital bit stream goes below the low frequency pole of the AC coupling

transformers then the droop characteristics of the transformers will dominate resulting in potentially

serious BLW.

The digital oscilloscope plot provided in Figure 7-5 illustrates the severity of the BLW event that can

theoretically be generated during 100BASE-TX packet transmission. This event consists of approximately

800 mV of DC offset for a period of 120 ms. Left uncompensated, events such as this can cause packet

loss.

7.2.3 Signal Detect

The signal detect function of the DP83848VYB is incorporated to meet the specifications mandated by the

ANSI FDDI TP-PMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage

thresholds and timing parameters.

Note that the reception of normal 10BASE-T link pulses and fast link pulses per IEEE 802.3u Auto-

Negotiation by the 100BASE-TX receiver do not cause the DP83848VYB to assert signal detect.

7.2.4 MLT-3 to NRZI Decoder

The DP83848VYB decodes the MLT-3 information from the Digital Adaptive Equalizer block to binary

NRZI data.

7.2.5 NRZI to NRZ

In a typical application, the NRZI to NRZ decoder is required in order to present NRZ formatted data to the

descrambler.

7.2.6 Serial to Parallel

The 100BASE-TX receiver includes a Serial to Parallel converter which supplies 5-bit wide data symbols

to the PCS Rx state machine.

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