Datasheet

DP83848VYB

www.ti.com

SNLS266D –MAY 2007–REVISED APRIL 2013

Table 6-1. Supported Packet Sizes at +/-50ppm +/-100ppm For Each Clock

Recommended Packet Size Recommended Packet Size

Start Threshold RBR[1:0] Latency Tolerance

at +/- 50ppm at +/- 100ppm

1 (4-bits) 2 bits 2,400 bytes 1,200 bytes

2 (8-bits) 6 bits 7,200 bytes 3,600 bytes

3 (12-bits) 10 bits 12,000 bytes 6,000 bytes

0 (16-bits) 14 bits 16,800 bytes 8,400 bytes

6.3 10 Mb SERIAL NETWORK INTERFACE (SNI)

The DP83848VYB incorporates a 10 Mb Serial Network Interface (SNI) which allows a simple serial data

interface for 10 Mb only devices. This is also referred to as a 7-wire interface. While there is no defined

standard for this interface, it is based on early 10 Mb physical layer devices. Data is clocked serially at 10

MHz using separate transmit and receive paths. The following pins are used in SNI mode:

— TX_CLK

— TX_EN

— TXD[0]

— RX_CLK

— RXD[0]

— CRS

— COL

6.4 802.3u MII SERIAL MANAGEMENT INTERFACE

6.4.1 Serial Management Register Access

The serial management MII specification defines a set of thirty-two 16-bit status and control registers that

are accessible through the management interface pins MDC and MDIO. The DP83848VYB implements all

the required MII registers as well as several optional registers. These registers are fully described in

6.4.2 Serial Management Access Protocol

The serial control interface consists of two pins, Management Data Clock (MDC) and Management Data

Input/Output (MDIO). MDC has a maximum clock rate of 25 MHz and no minimum rate. The MDIO line is

bi-directional and may be shared by up to 32 devices. The MDIO frame format is shown below in

Table 6-2.

Table 6-2. Typical MDIO Frame Format

MII Management Serial Protocol <idle><start><op code><device addr><reg addr><turnaround><data><idle>

Read Operation <idle><01><10><AAAAA><RRRRR><Z0><xxxx xxxx xxxx xxxx><idle>

Write Operation <idle><01><01><AAAAA><RRRRR><10><xxxx xxxx xxxx xxxx><idle>

The MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high.

In order to initialize the MDIO interface, the station management entity sends a sequence of 32 contiguous

logic ones on MDIO to provide the DP83848VYB with a sequence that can be used to establish

synchronization. This preamble may be generated either by driving MDIO high for 32 consecutive MDC

clock cycles, or by simply allowing the MDIO pull-up resistor to pull the MDIO pin high during which time

32 MDC clock cycles are provided. In addition 32 MDC clock cycles should be used to re-sync the device

if an invalid start, opcode, or turnaround bit is detected.

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