Datasheet

DP83848VYB
SNLS266D –MAY 2007–REVISED APRIL 2013 www.ti.com
4.29 AC Specifications — RMII Transmit Timing
Parameter Description Notes Min Typ Max Units
T2.26.1 X1 Clock Period 50 MHz Reference Clock 20 ns
T2.26.2 TXD[1:0], TX_EN, Data Setup to X1 rising 4 ns
T2.26.3 TXD[1:0], TX_EN, Data Hold from X1 rising 2 ns
T2.26.4 X1 Clock to PMD Output Pair Latency From X1 Rising edge to first bit of 17 bits
symbol
4.30 AC Specifications — RMII Receive Timing
Parameter Description Notes Min Typ Max Units
T2.27.1 X1 Clock Period 50 MHz Reference Clock 20 ns
T2.27.2 RXD[1:0], CRS_DV, RX_DV and 2 14 ns
RX_ER output delay from X1
rising
(1)(2)(3)
T2.27.3 CRS ON delay (100Mb) From JK symbol on PMD Receive 18.5 bits
Pair to initial assertion of
CRS_DV
T2.27.4 CRS OFF delay (100Mb) From TR symbol on PMD 27 bits
Receive Pair to initial deassertion
of CRS_DV
T2.27.5 RXD[1:0] and RX_ER latency From symbol on Receive Pair. 38 bits
(100Mb) Elasticity buffer set to default
value (01)
(1) Per the RMII Specification, output delays assume a 25pF load.
(2) CRS_DV is asserted asynchronously in order to minimize latency of control signals through the Phy. CRS_DV may toggle
synchronously at the end of the packet to indicate CRS deassertion.
(3) RX_DV is synchronous to X1. While not part of the RMII specification, this signal is provided to simplify recovery of receive data.
28 Electrical Specifications Copyright © 2007–2013, Texas Instruments Incorporated
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