Datasheet

DP83848VYB
SNLS266D –MAY 2007–REVISED APRIL 2013 www.ti.com
4.14 AC Specifications — 10 Mb/s MII Transmit Timing
Parameter Description Notes
(1)
Min Typ Max Units
T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns
T2.11.2 TXD[3:0], TX_EN Data Setup to 10 Mb/s MII mode 25 ns
TX_CLK fall
T2.11.3 TXD[3:0], TX_EN Data Hold from 10 Mb/s MII mode 0 ns
TX_CLK rise
(1) An attached Mac should drive the transmit signals using the positive edge of TX_CLK. As shown above, the MII signals are sampled on
the falling edge of TX_CLK.
4.15 AC Specifications — 10 Mb/s MII Receive Timing
Parameter Description Notes Min Typ Max Units
T2.12.1 RX_CLK High/Low Time
(1)
160 200 240 ns
T2.12.2 RX_CLK TO RXD[3:0}, RX_DV Delay 10 Mb/s MII mode 100 ns
T2.12.3 RX_CLK rising edge delay from RXD[3:0], RX_DV 10 Mb/s MII mode 100 ns
Valid
(1) RX_CLK may be held low for a longer period of time during transition between reference and recovered clocks. Minimum high and low
times will not be violated.
20 Electrical Specifications Copyright © 2007–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: DP83848VYB