Datasheet

DP83848VYB
SNLS266D –MAY 2007–REVISED APRIL 2013 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4.21 AC Specifications — 10BASE-T Receive Timing
1 Introduction .............................................. 1
(End of Packet) ..................................... 23
1.1 Features ............................................. 1
4.22 AC Specifications — 10 Mb/s Heartbeat Timing ... 24
1.2 Applications .......................................... 1
4.23 AC Specifications — 10 Mb/s Jabber Timing ...... 24
1.3 Description ........................................... 1
4.24 AC Specifications — 10BASE-T Normal Link Pulse
2 Device Information ...................................... 3
Timing .............................................. 24
2.1 System Diagram ..................................... 3
4.25 AC Specifications — Auto-Negotiation Fast Link
2.2 Block Diagram ....................................... 4
Pulse (FLP) Timing ................................. 25
3 Pin Descriptions ......................................... 5
4.26 AC Specifications — 100BASE-TX Signal Detect
Timing .............................................. 25
3.1 Pin Layout ........................................... 6
4.27 AC Specifications — 100 Mb/s Internal Loopback
3.2 PACKAGE PIN ASSIGNMENTS .................... 7
Timing .............................................. 26
3.3 SERIAL MANAGEMENT INTERFACE .............. 8
4.28 AC Specifications — 10 Mb/s Internal Loopback
3.4 MAC DATA INTERFACE ............................ 8
Timing .............................................. 27
3.5 CLOCK INTERFACE ................................ 9
4.29 AC Specifications — RMII Transmit Timing ........ 28
3.6 LED INTERFACE .................................... 9
4.30 AC Specifications — RMII Receive Timing ........ 28
3.7 JTAG INTERFACE .................................. 9
4.31 AC Specifications — Isolation Timing .............. 29
3.8 RESET AND POWER DOWN ...................... 10
4.32 AC Specifications — 25 MHz_OUT Timing ........ 29
3.9 STRAP OPTIONS .................................. 10
4.33 AC Specifications — 100 Mb/s X1 to TX_CLK
3.10 10 Mb/s AND 100 Mb/s PMD INTERFACE ........ 11
Timing .............................................. 29
3.11 SPECIAL CONNECTIONS ......................... 11
5 Configuration ........................................... 30
3.12 POWER SUPPLY PINS ........................... 11
5.1 AUTO-NEGOTIATION .............................. 30
4 Electrical Specifications ............................. 12
5.2 AUTO-MDIX ........................................ 32
4.1 Absolute Maximum Ratings ........................ 12
5.3 PHY ADDRESS .................................... 33
4.2 Recommended Operating Conditions .............. 12
5.4 LED INTERFACE ................................... 34
4.3 AC and DC Specifications .......................... 12
5.5 HALF DUPLEX vs. FULL DUPLEX ................ 35
4.4 AC Specifications — Power Up Timing ............ 14
5.6 INTERNAL LOOPBACK ............................ 36
4.5 AC Specifications — Reset Timing ................. 15
5.7 BIST ................................................ 36
4.6 AC Specifications — MII Serial Management Timing
6 Functional Description ............................... 37
...................................................... 16
6.1 MII INTERFACE .................................... 37
4.7 AC Specifications — 100 Mb/s MII Transmit Timing
6.2 REDUCED MII INTERFACE ....................... 38
...................................................... 16
6.3 10 Mb SERIAL NETWORK INTERFACE (SNI) .... 39
4.8 AC Specifications — 100 Mb/s MII Receive Timing 17
6.4 802.3u MII SERIAL MANAGEMENT INTERFACE 39
4.9 AC Specifications — 100BASE-TX and 100BASE-
7 Architecture ............................................. 41
FX MII Transmit Packet Latency Timing ........... 17
7.1 100BASE-TX TRANSMITTER ...................... 41
4.10 AC Specifications — 100BASE-TX Transmit Packet
Deassertion Timing ................................. 18
7.2 100BASE-TX RECEIVER .......................... 43
4.11 AC Specifications — 100BASE-TX Transmit Timing
7.3 10BASE-T TRANSCEIVER MODULE .............. 48
(t
R/F
& Jitter) ........................................ 18
8 Reset Operation ........................................ 51
4.12 AC Specifications — 100BASE-TX Receive Packet
8.1 HARDWARE RESET ............................... 51
Latency Timing ..................................... 19
8.2 SOFTWARE RESET ............................... 51
4.13 AC Specifications — 100BASE-TX Receive Packet
Deassertion Timing ................................. 19 9 Design Guidelines ..................................... 52
4.14 AC Specifications — 10 Mb/s MII Transmit Timing 20 9.1 TPI NETWORK CIRCUIT .......................... 52
4.15 AC Specifications — 10 Mb/s MII Receive Timing . 20 9.2 ESD PROTECTION ................................ 52
4.16 AC Specifications — 10 Mb/s Serial Mode Transmit
9.3 CLOCK IN (X1) REQUIREMENTS ................. 52
Timing .............................................. 21
9.4 POWER FEEDBACK CIRCUIT .................... 55
4.17 AC Specifications — 10 Mb/s Serial Mode Receive
9.5 POWER DOWN/INTERRUPT ...................... 55
Timing .............................................. 21
9.6 ENERGY DETECT MODE ......................... 56
4.18 AC Specifications — 10BASE-T Transmit Timing
9.7 THERMAL Vias RECOMMENDATION ............. 56
(Start of Packet) .................................... 22
10 Register Block ......................................... 57
4.19 AC Specifications — 10BASE-T Transmit Timing
(End of Packet) ..................................... 22
10.1 Register Block ...................................... 57
4.20 AC Specifications — 10BASE-T Receive Timing
Revision History ............................................ 77
(Start of Packet) .................................... 23
2 Contents Copyright © 2007–2013, Texas Instruments Incorporated
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