Datasheet

DP83848VYB
SNLS266D –MAY 2007–REVISED APRIL 2013 www.ti.com
4.10 AC Specifications — 100BASE-TX Transmit Packet Deassertion Timing
Parameter Description Notes Min Typ Max Units
T2.7.1 TX_CLK to PMD Output Pair 100BASE-TX and 100BASE-FX modes 5 bits
Deassertion
(1)
(1) Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the
first bit of the “T” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
4.11 AC Specifications — 100BASE-TX Transmit Timing (t
R/F
& Jitter)
Parameter Description Notes Min Typ Max Units
T2.8.1 100 Mb/s PMD Output Pair t
R
and t
F
(1)
3 4 5 ns
100 Mb/s t
R
and t
F
Mismatch
(2)(1)
500 ps
T2.8.2 100 Mb/s PMD Output Pair Transmit Jitter 1.4 ns
(1) Rise and fall times taken at 10% and 90% of the +1 or -1 amplitude
(2) Normal Mismatch is the difference between the maximum and minimum of all rise and fall times
18 Electrical Specifications Copyright © 2007–2013, Texas Instruments Incorporated
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