Datasheet

DP83848VYB
www.ti.com SNLS266D –MAY 2007–REVISED APRIL 2013
4.8 AC Specifications — 100 Mb/s MII Receive Timing
Parameter Description Notes Min Typ Max Units
T2.5.1 RX_CLK High/Low Time
(1)
100 Mb/s Normal mode 16 20 24 ns
T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER 100 Mb/s Normal mode 10 30 ns
Delay
(1) RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high
and low times will not be violated.
4.9 AC Specifications — 100BASE-TX and 100BASE-FX MII Transmit Packet Latency
Timing
Parameter Description Notes Min Typ Max Units
T2.6.1 TX_CLK to PMD Output Pair Latency
(1)
100BASE-TX and 100BASE-FX modes 6 bits
(1) For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of
TX_EN to the first bit of the “J” code group as output from the PMD Output Pair. 1 bit time = 10 ns in 100 Mb/s mode.
Copyright © 2007–2013, Texas Instruments Incorporated Electrical Specifications 17
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