Datasheet

DP83848VYB
www.ti.com SNLS266D –MAY 2007–REVISED APRIL 2013
Signal Name Type Pin # Description
MII_MODE (RX_DV) S, O, PD 39 MII MODE SELECT: This strapping option pair determines the operating mode of the
SNI_MODE (TXD_3) 6 MAC Data Interface. Default operation (No pull-ups) will enable normal MII Mode of
operation. Strapping MII_MODE high will cause the device to be in RMII or SNI modes of
operation, determined by the status of the SNI_MODE strap. Since the pins include
internal pull-downs, the default values are 0.
The following table details the configurations:
MII_MODE SNI_MODE MAC Interface Mode
0 X MII Mode
1 0 RMII Mode
1 1 10 Mb SNI Mode
LED_CFG (CRS) S, O, PU 40 LED CONFIGURATION: This strapping option determines the mode of operation of the
LED pins. Default is Mode 1. Mode 1 and Mode 2 can be controlled via the strap option.
All modes are configurable via register access.
See Table 5-3 for LED Mode Selection.
MDIX_EN (RX_ER) S, O, PU 41 MDIX ENABLE: Default is to enable MDIX. This strapping option disables Auto-MDIX. An
external pull-down will disable Auto-MDIX mode.
3.10 10 Mb/s AND 100 Mb/s PMD INTERFACE
Signal Name Type Pin # Description
TD-, TD+ I/O 16 Differential common driver transmit output (PMD Output Pair). These differential outputs
17 are automatically configured to either 10BASE-T or 100BASE-TX signaling.
IIn Auto-MDIX mode of operation, this pair can be used as the Receive Input pair.
These pins require 3.3V bias for operation.
RD-, RD+ I/O 13 Differential receive input (PMD Input Pair). These differential inputs are automatically
14 configured to accept either 100BASE-TX or 10BASE-T signaling.
In Auto-MDIX mode of operation, this pair can be used as the Transmit Output pair.
In 100BASE-FX mode, this pair becomes the 100BASE-FX Receive pair.
These pins require 3.3V bias for operation.
3.11 SPECIAL CONNECTIONS
Signal Name Type Pin # Description
RBIAS I 24 Bias Resistor Connection: A 4.87 kΩ 1% resistor should be connected from RBIAS to
GND.
PFBOUT O 23 Power Feedback Output: Parallel caps, 10µF (Tantalum preferred) and 0.1µF, should be
placed close to the PFBOUT. Connect this pin to PFBIN1 (pin 18) and PFBIN2 (pin 37). See
Section POWER FEEDBACK CIRCUIT for proper placement pin.
PFBIN1 I 18 Power Feedback Input: These pins are fed with power from PFBOUT pin. A small capacitor
PFBIN2 37 of 0.1µF should be connected close to each pin.
(1)
RESERVED I/O 20, 21 RESERVED: These pins must be pulled-up through 2.2 kΩ resistors to AVDD33 supply.
(1) Note: Do not supply power to these pins other than from PFBOUT.
3.12 POWER SUPPLY PINS
Signal Name Pin # Description
IOVDD33 32, 38 I/O 3.3V Supply
IOGND 35, 47 I/O Ground
DGND 36 Digital Ground
AVDD33 22 Analog 3.3V Supply
AGND 15, 19 Analog Ground
GNDPAD 49 Ground PAD
Copyright © 2007–2013, Texas Instruments Incorporated Pin Descriptions 11
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