Datasheet

DP83848VYB
SNLS266D –MAY 2007–REVISED APRIL 2013 www.ti.com
3.8 RESET AND POWER DOWN
Signal Name Type Pin # Description
RESET_N I, PU 29 RESET: Active Low input that initializes or re-initializes the DP83848VYB. Asserting
this pin low for at least 1 µs will force a reset process to occur. All internal registers
will re-initialize to their default states as specified for each bit in the Register Block
section. All strap options are re-initialized as well.
PWR_DOWN/INT I, PU 7 See Section POWER DOWN/INTERRUPT for detailed description.
The default function of this pin is POWER DOWN.
POWER DOWN: The pin is an active low input in this mode and should be
asserted low to put the device in a Power Down mode.
INTERRUPT: The pin is an open drain output in this mode and will be asserted low
when an interrupt condition occurs. Although the pin has a weak internal pull-up,
some applications may require an external pull-up resister. Register access is
required for the pin to be used as an interrupt mechanism. See Section Interrupt
Mechanisms for more details on the interrupt mechanisms.
3.9 STRAP OPTIONS
The DP83848VYB uses many of the functional pins as strap options. The values of these pins are
sampled during reset and used to strap the device into specific modes of operation. The strap option pin
assignments are defined below. The functional pin name is indicated in parentheses.
A 2.2 kΩ resistor should be used for pull-down or pull-up to change the default strap option. If the default
option is required, then there is no need for external pull-up or pull down resistors. Since these pins may
have alternate functions after reset is deasserted, they should not be connected directly to V
CC
or GND.
Signal Name Type Pin # Description
PHYAD0 (COL) S, O, PU 42 PHY ADDRESS [4:0]: The DP83848VYB provides five PHY address pins, the state of
PHYAD1 (RXD1_0) S, O, PD 43 which are latched into the PHYCTRL register at system Hardware-Reset.
PHYAD2 (RXD0_1) 44 The DP83848VYB supports PHY Address strapping values 0 (<00000>) through 31
PHYAD3 (RXD1_2) 45 (<11111>).A PHY Adress of 0 puts the part into the Mll isolate Mode. The Mll isolate
PHYAD4 (RXD1_3) 46 mode must be selected by strapping Phy Address 0; changing to Address 0 by register
write will not put the Phy in the Mll isolate mode. Please refer to section PHY ADDRESS
for additional information.
PHYAD0 pin has weak internal pull-up resistor.
PHYAD[4:1] pins have weak internal pull-up resistors.
AN_EN(LED_ACT/COL) S, O, PU 26 Auto-Negotiation Enable: When high, this enables Auto-Negotiation with the capability
AN_1 (LED_SPEED) 27 set by AN0 and AN1 pins. When low, this puts the part into Forced Mode with the
AN_0 (LED_LINK) 28 capability set by AN0 and AN1 pins.
AN0 / AN1: These input pins control the forced or advertised operating mode of the
DP83848VYB according to the following table. The value on these pins is set by
connecting the input pins to GND (0) or V
CC
(1) through 2.2 kΩ resistors. These pins
should NEVER be connected directly to GND or V
CC
.
The value set at this input is latched into the DP83848VYB at Hardware-Reset.
The float/pull-down status of these pins are latched into the Basic Mode Control Register
and the Auto_Negotiation Advertisement Register during Hardware-Reset.
The default is 111 since the these pin have internal pull-ups.
AN_EN AN1 AN0 Forced Mode
0 0 0 10BASE-T, Half-Duplex
0 0 1 10BASE-T, Full-Duplex
0 1 0 100BASE-TX, Half-Duplex
0 1 1 100BASE-TX, Full-Duplex
AN_EN AN1 AN0 Advertised Mode
1 0 0 10BASE-T, Half/Full-Duplex
1 0 1 100BASE-TX, Half/Full-Duplex
1 1 0 10BASE-T, Half-Duplex,
100BASE-TX, Half-Duplex
1 1 1 10BASE-T, Half/Full-Duplex,
100BASE-TX, Half/Full-Duplex
10 Pin Descriptions Copyright © 2007–2013, Texas Instruments Incorporated
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