Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - transceivers Ethernet 1/1 LQFP 48 EP

DP83848VYB

www.ti.com

SNLS266D –MAY 2007–REVISED APRIL 2013

DP83848VYB PHYTER™ - Extended Temperature Single Port 10/100 Mb/s Ethernet

Physical Layer Transceiver

Check for Samples: DP83848VYB

1 Introduction

1.1 Features

123

and Filters

• Extreme Temperature from -40°C to 105°C

• IEEE 802.3u PCS, 100BASE-TX Transceivers

• Low-Power 3.3V, 0.18µm CMOS Technology

and Filters

• Low Power Consumption <270mW Typical

• IEEE 1149.1 JTAG

• 3.3V MAC Interface

• Integrated ANSI X3.263 Compliant TP-PMD

• Auto-MDIX for 10/100 Mb/s

Physical Sub-Layer with Adaptive Equalization

• Energy Detection Mode

and Baseline Wander Compensation

• 25 MHz Clock Out

• Error-Free Operation up to 150 Meters

• SNI Interface (Configurable)

• Programmable LED Support for Link, 10 /100

• RMII Rev. 1.2 Interface (Configurable)

Mb/s Mode, Activity, Duplex and Collision

• MII Serial Management Interface (MDC and

Detect

MDIO)

• Single Register Access for Complete PHY

• IEEE 802.3u MII

Status

• IEEE 802.3u Auto-Negotiation and Parallel

• 10/100 Mb/s Packet BIST (Built in Self Test)

Detection

• Lead Free 48-Pin HLQFP Package (7mm) x

• IEEE 802.3u ENDEC, 10BASE-T Transceivers

(7mm) ADC

1.2 Applications

• Automotive/Transportation

• Industrial Controls and Factory Automation

• General Embedded Applications

1.3 Description

The number of applications requiring Ethernet connectivity continues to increase, driving Ethernet enabled

devices into harsher environments.

The DP83848VYB was designed to meet the challenge of these new applications with an extended

temperature performance that goes beyond the typical Industrial temperature range. The DP83848VYB is

a highly reliable, feature rich, robust device which meets IEEE 802.3u standards over an EXTENDED

temperature range of -40°C to 105°C. This device is ideally suited for harsh environments such as

wireless remote base stations, automotive/transportation, and industrial control applications.

It offers enhanced ESD protection and the choice of an MII or RMII interface for maximum flexibility in

MPU selection; all in a 48 pin HLQFP package.

The DP83848VYB extends the leadership position of the PHYTER™ family of devices with a wide

operating temperature range. The TI line of PHYTER transceivers builds on decades of Ethernet expertise

to offer the high performance and flexibility that allows the end user an easy implementation tailored to

meet these application needs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PHYTER is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products conform to

specifications per the terms of the Texas Instruments standard warranty. Production

processing does not necessarily include testing of all parameters.

Summary of content (80 pages)

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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 DP83848VYB PHYTER™ - Extended Temperature Single Port 10/100 Mb/s Ethernet Physical Layer Transceiver Check for Samples: DP83848VYB 1 Introduction 1.1 Features 123 • • • • • • • • • • Extreme Temperature from -40°C to 105°C Low-Power 3.3V, 0.18µm CMOS Technology Low Power Consumption <270mW Typical 3.3V MAC Interface Auto-MDIX for 10/100 Mb/s Energy Detection Mode 25 MHz Clock Out SNI Interface (Configurable) RMII Rev. 1.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 .............................................. 1 ............................................. 1 1.2 Applications .......................................... 1 1.3 Description ...........................................
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 2 Device Information 2.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 2.2 Block Diagram 4 Device Information www.ti.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 3 Pin Descriptions The DP83848VYB pins are classified into the following interface categories (each interface is described in the sections that follow): • Serial Management Interface • MAC Data Interface • Clock Interface • LED Interface • JTAG Interface • Reset and Power Down • Strap Options • 10/100 Mb/s PMD Interface • Special Connect Pins • Power and Ground pins NOTE Strapping pin option.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 3.1 www.ti.com Pin Layout Figure 3-1.
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DP83848VYB www.ti.com 3.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 3.3 www.ti.com SERIAL MANAGEMENT INTERFACE Signal Name Type Pin # MDC I 31 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data input/output serial interface which may be asynchronous to transmit and receive clocks. The maximum clock rate is 25 MHz with no minimum clock rate. MDIO I/O 30 MANAGEMENT DATA I/O: Bi-directional management instruction/data signal that may be sourced by the station management entity or the PHY.
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DP83848VYB www.ti.com Signal Name COL 3.5 SNLS266D – MAY 2007 – REVISED APRIL 2013 Type Pin # S, O, PU 42 Description MII COLLISION DETECT: Asserted high to indicate detection of a collision condition (simultaneous transmit and receive activity) in 10 Mb/s and 100 Mb/s Half Duplex Modes. While in 10BASE-T Half Duplex mode with heartbeat enabled this pin is also asserted for a duration of approximately 1µs at the end of transmission to indicate heartbeat (SQE test).
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 3.8 www.ti.com RESET AND POWER DOWN Signal Name Type Pin # Description RESET_N I, PU 29 RESET: Active Low input that initializes or re-initializes the DP83848VYB. Asserting this pin low for at least 1 µs will force a reset process to occur. All internal registers will re-initialize to their default states as specified for each bit in the Register Block section. All strap options are re-initialized as well.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Signal Name MII_MODE (RX_DV) SNI_MODE (TXD_3) Type Pin # Description S, O, PD 39 6 MII MODE SELECT: This strapping option pair determines the operating mode of the MAC Data Interface. Default operation (No pull-ups) will enable normal MII Mode of operation. Strapping MII_MODE high will cause the device to be in RMII or SNI modes of operation, determined by the status of the SNI_MODE strap.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 4 Electrical Specifications 4.1 Absolute Maximum Ratings (1) (2) Supply Voltage (VCC) -0.5 V to 4.2 V DC Input Voltage (VIN) -0.5V to VCC + 0.5V DC Output Voltage (VOUT) -0.5V to VCC + 0.5V Storage Temperature (TSTG ) -65°C to 150°C Max. Die Temperature 121.5°C Lead Temp. (TL) (Soldering, 10 sec.) 260 °C ESD Rating (RZAP = 1.5k, CZAP = 100 pF) 4.
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DP83848VYB www.ti.com 4.3.1 SNLS266D – MAY 2007 – REVISED APRIL 2013 DC Specifications Symbol VIH Pin Types I, Parameter Conditions Input High Voltage Min Nominal VCC Typ Max 2.0 Units V I/O VIL I, Input Low Voltage 0.8 V I/O IIH I, Input High Current VIN = VCC 10 µA Input Low Current VIN = GND 10 µA IOL = 4 mA 0.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 4.4 www.ti.com AC Specifications — Power Up Timing Parameter T2.1.1 T2.1.2 Notes Min Post Power Up Stabilization time prior to MDC preamble for register accesses (1) Description MDIO is pulled high for 32-bit serial management initialization 167 Typ Max Units ms Hardware Configuration Latch-in Time from power up (1) Hardware Configuration Pins are described in the Pin Description section. 167 ms X1 Clock must be stable for a min.
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DP83848VYB www.ti.com 4.5 SNLS266D – MAY 2007 – REVISED APRIL 2013 AC Specifications — Reset Timing Parameter Description Notes Min Typ Max Units T2.2.1 Post RESET Stabilization time prior to MDC preamble for register accesses (1) MDIO is pulled high for 32-bit serial management initialization 3 µs T2.2.2 Hardware Configuration Latch-in Time from the Deassertion of RESET (either soft or hard) (1) Hardware Configuration Pins are described in the Pin Description section 3 µs T2.2.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 4.6 www.ti.com AC Specifications — MII Serial Management Timing Parameter Description Notes Min T2.3.1 MDC to MDIO (Output) Delay Time 0 T2.3.2 MDIO (Input) to MDC Setup Time 10 T2.3.3 MDIO (Input) to MDC Hold Time 10 T2.3.4 MDC Frequency 4.7 Typ Max Units 30 ns ns ns 2.5 25 MHz AC Specifications — 100 Mb/s MII Transmit Timing Min Typ Max Units T2.4.
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DP83848VYB www.ti.com 4.8 SNLS266D – MAY 2007 – REVISED APRIL 2013 AC Specifications — 100 Mb/s MII Receive Timing Min Typ Max Units T2.5.1 Parameter RX_CLK High/Low Time (1) 100 Mb/s Normal mode 16 20 24 ns T2.5.2 RX_CLK to RXD[3:0], RX_DV, RX_ER Delay 100 Mb/s Normal mode 10 30 ns (1) Notes RX_CLK may be held low or high for a longer period of time during transition between reference and recovered clocks. Minimum high and low times will not be violated. 4.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 4.10 AC Specifications — 100BASE-TX Transmit Packet Deassertion Timing Parameter T2.7.1 (1) Description Notes TX_CLK to PMD Output Pair Deassertion (1) Min 100BASE-TX and 100BASE-FX modes Typ Max 5 Units bits Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the “T” code group as output from the PMD Output Pair.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 4.12 AC Specifications — 100BASE-TX Receive Packet Latency Timing Parameter T2.9.1 T2.9.2 (1) (2) (3) Description Carrier Sense ON Delay (2) Receive Data Latency Notes (1) Min Typ Max Units 100 Mb/s Normal mode (3) 20 bits (3) 24 bits 100 Mb/s Normal mode PMD Input Pair voltage amplitude is greater than the Signal Detect Turn-On Threshold Value.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 4.14 AC Specifications — 10 Mb/s MII Transmit Timing Parameter Notes (1) Min Typ Max Units T2.11.1 TX_CLK High/Low Time 10 Mb/s MII mode 190 200 210 ns T2.11.2 TXD[3:0], TX_EN Data Setup to TX_CLK fall 10 Mb/s MII mode 25 ns T2.11.3 TXD[3:0], TX_EN Data Hold from TX_CLK rise 10 Mb/s MII mode 0 ns (1) Description An attached Mac should drive the transmit signals using the positive edge of TX_CLK.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 4.16 AC Specifications — 10 Mb/s Serial Mode Transmit Timing Min Typ Max Units T2.13.1 Parameter TX_CLK High Time Description 10 Mb/s Serial mode Notes 20 25 30 ns T2.13.2 TX_CLK Low Time 10 Mb/s Serial mode 70 75 80 ns T2.13.3 TXD_0, TX_EN Data Setup to TX_CLK rise 10 Mb/s Serial mode 25 ns T2.13.4 TXD_0, TX_EN Data Hold from TX_CLK rise 10 Mb/s Serial mode 0 ns 4.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 4.18 AC Specifications — 10BASE-T Transmit Timing (Start of Packet) Parameter T2.15.1 Description Transmit Output Delay from the Notes Min Typ Max Units 10 Mb/s MII mode (1) 3.5 bits 10 Mb/s Serial mode (1) 3.5 bits Falling Edge of TX_CLK T2.15.2 Transmit Output Delay from the Rising Edge of TX_CLK (1) 1 bit time = 100 ns in 10 Mb/s. TX_CLK TX_EN TXD T2.15.2 PMD Output Pair T2.15.1 4.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 4.20 AC Specifications — 10BASE-T Receive Timing (Start of Packet) Parameter Notes (1) Description T2.17.1 Carrier Sense Turn On Delay (PMD Input Pair to CRS) T2.17.2 RX_DV Latency (2) T2.17.3 Receive Data Latency (1) (2) Min Typ Max Units 630 1000 ns Measurement shown from SFD 10 bits 8 bits 1 bit time = 100 ns in 10 Mb/s mode.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 4.22 AC Specifications — 10 Mb/s Heartbeat Timing Parameter Description Notes Min Typ Max Units T2.19.1 CD Heartbeat Delay 10 Mb/s half-duplex mode 1200 ns T2.19.2 CD Heartbeat Duration 10 Mb/s half-duplex mode 1000 ns 4.23 AC Specifications — 10 Mb/s Jabber Timing Parameter Description Notes Min Typ Max Units T2.20.1 Jabber Activation Time 85 ms T2.20.2 Jabber Deactivation Time 500 ms 4.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 4.25 AC Specifications — Auto-Negotiation Fast Link Pulse (FLP) Timing Parameter Notes (1) Description Min Typ Max Units T2.22.1 Clock, Data Pulse Width 100 ns T2.22.2 Clock Pulse to Clock Pulse 125 µs 62 µs Period T2.22.3 Clock Pulse to Data Pulse Data = 1 Period T2.22.4 Burst Width 2 ms T2.22.5 FLP Burst to FLP Burst Period 16 ms (1) These specifications represent transmit timings. 4.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 4.27 AC Specifications — 100 Mb/s Internal Loopback Timing Parameter Description TX_EN to RX_DV Loopback (1) T2.24.1 (1) (2) 26 Notes 100 Mb/s internal loopback mode (2) Min Typ Max Units 240 ns Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 4.28 AC Specifications — 10 Mb/s Internal Loopback Timing Parameter T2.25.1 (1) Description TX_EN to RX_DV Loopback (1) Notes 10 Mb/s internal loopback mode Min Typ Max Units 2 µs Measurement is made from the first rising edge of TX_CLK after assertion of TX_EN.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 4.29 AC Specifications — RMII Transmit Timing Parameter Description Notes Min T2.26.1 X1 Clock Period T2.26.2 TXD[1:0], TX_EN, Data Setup to X1 rising 4 T2.26.3 TXD[1:0], TX_EN, Data Hold from X1 rising 2 T2.26.4 X1 Clock to PMD Output Pair Latency Typ 50 MHz Reference Clock Max Units 20 ns ns ns From X1 Rising edge to first bit of symbol 17 bits 4.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 4.31 AC Specifications — Isolation Timing Max Units T2.28.1 Parameter From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal mode Description Notes Min Typ 100 µs T2.28.2 From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 500 µs Max Units 4.32 AC Specifications — 25 MHz_OUT Timing Parameter T2.29.1 T2.29.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 5 Configuration This section includes information on the various configuration options available with the DP83848VYB. The configuration options described below include: — Auto-Negotiation — PHY Address and LEDs — Half Duplex vs. Full Duplex — Isolate mode — Loopback mode — BIST 5.
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DP83848VYB www.ti.com 5.1.2 SNLS266D – MAY 2007 – REVISED APRIL 2013 Auto-Negotiation Register Control When Auto-Negotiation is enabled, the DP83848VYB transmits the abilities programmed into the AutoNegotiation Advertisement register (ANAR) at address 04h via FLP Bursts. Any combination of 10 Mb/s, 100 Mb/s, Half-Duplex, and Full Duplex modes may be selected. Auto-Negotiation Priority Resolution: 1. 100BASE-TX Full Duplex (Highest Priority) 2. 100BASE-TX Half Duplex 3. 10BASE-T Full Duplex 4.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com If the DP83848VYB completes Auto-Negotiation as a result of Parallel Detection, bits 5 and 7 within the ANLPAR register will be set to reflect the mode of operation present in the Link Partner. Note that bits 4:0 of the ANLPAR will also be set to 00001 based on a successful parallel detection to indicate a valid 802.3 selector field.
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DP83848VYB www.ti.com 5.3 SNLS266D – MAY 2007 – REVISED APRIL 2013 PHY ADDRESS The 5 PHY address inputs pins are shared with the RXD[3:0] pins and COL pin are shown below. Table 5-2. PHY Address Mapping Pin # PHYAD Function 42 PHYAD0 RXD Function COL 43 PHYAD1 RXD_0 44 PHYAD2 RXD_1 45 PHYAD3 RXD_2 46 PHYAD4 RXD_3 The DP83848VYB can be set to respond to any of 32 possible PHY addresses via strap pins.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com The DP83848VYB can Auto-Negotiate or parallel detect to a specific technology depending on the receive signal at the PMD input pair. A valid link can be established for the receiver even when the DP83848VYB is in Isolate mode. 5.4 LED INTERFACE The DP83848VYB supports three configurable Light Emitting Diode (LED) pins. The device supports three LED configurations: Link, Speed, Activity and Collision. Function are multiplexed among the LEDs.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Refer to Figure 5-2 for an example of AN connections to external components. In this example, the AN strapping results in Auto-Negotiation disabled with 10/100 Half/Full-Duplex advertised . The adaptive nature of the LED outputs helps to simplify potential implementation issues of these dual purpose pins. Figure 5-2. AN Strapping and LED Loading Example 5.4.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 5.6 www.ti.com INTERNAL LOOPBACK The DP83848VYB includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3 of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be transmitted onto the media.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 6 Functional Description The DP83848VYB supports several modes of operation using the MII interface pins. The options are defined in the following sections and include: — MII Mode — RMII Mode — 10 Mb Serial Network Interface (SNI) The modes of operation can be selected by strap options or register control. For RMII mode, it is required to use the strap option, since it requires a 50 MHz clock instead of the normal 25 MHz.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com When heartbeat is enabled (only applicable to 10 Mb/s operation), approximately 1µs after the transmission of each packet, a Signal Quality Error (SQE) signal of approximately 10 bit times is generated (internally) to indicate successful transmission. SQE is reported as a pulse on the COL signal of the MII. 6.1.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Table 6-1. Supported Packet Sizes at +/-50ppm +/-100ppm For Each Clock Start Threshold RBR[1:0] Latency Tolerance Recommended Packet Size at +/- 50ppm Recommended Packet Size at +/- 100ppm 1 (4-bits) 2 bits 2,400 bytes 1,200 bytes 2 (8-bits) 6 bits 7,200 bytes 3,600 bytes 3 (12-bits) 10 bits 12,000 bytes 6,000 bytes 0 (16-bits) 14 bits 16,800 bytes 8,400 bytes 6.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com The DP83848VYB waits until it has received this preamble sequence before responding to any other transaction. Once the DP83848VYB serial management port has been initialized no further preamble sequencing is required until after a power-on/reset, invalid Start, invalid Opcode, or invalid turnaround bit has occurred. The Start code is indicated by a <01> pattern. This assures the MDIO line transitions from the default idle line state.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 7 Architecture This section describes the operations within each transceiver module, 100BASE-TX and 10BASE-T. Each operation consists of several functional blocks and described in the following: — 100BASE-TX Transmitter — 100BASE-TX Receiver — 10BASE-T Transceiver Module 7.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com Table 7-1.
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DP83848VYB www.ti.com 7.1.2 SNLS266D – MAY 2007 – REVISED APRIL 2013 Scrambler The scrambler is required to control the radiated emissions at the media connector and on the twisted pair cable (for 100BASE-TX applications). By scrambling the data, the total energy launched onto the cable is randomly distributed over a wide frequency range. Without the scrambler, energy levels at the PMD and on the cable could peak beyond FCC limitations at frequencies related to repeating 5B sequences (i.e.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com — Link Integrity Monitor — Bad SSD Detection 7.2.1 Analog Front End In addition to the Digital Equalization and Gain Control, the DP83848VYB includes Analog Equalization and Gain Control in the Analog Front End. The Analog Equalization reduces the amount of Digital Equalization required in the DSP. 7.2.2 Digital Signal Processor The Digital Signal Processor includes Adaptive Equalization with Gain Control and Base Line Wander Compensation.
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DP83848VYB www.ti.com 7.2.2.1 SNLS266D – MAY 2007 – REVISED APRIL 2013 Digital Adaptive Equalization and Gain Control When transmitting data at high speeds over copper twisted pair cable, frequency dependent attenuation becomes a concern. In high-speed twisted pair signalling, the frequency content of the transmitted signal can vary greatly during normal operation based primarily on the randomness of the scrambled data stream.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 7.2.2.2 www.ti.com Base Line Wander Compensation Figure 7-4. 100BASE-TX BLW Event The DP83848VYB is completely ANSI TP-PMD compliant and includes Base Line Wander (BLW) compensation. The BLW compensation block can successfully recover the TP-PMD defined “killer” pattern. BLW can generally be defined as the change in the average DC content, relatively short period over time, of an AC coupled digital transmission over a given transmission medium. (i.e.
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DP83848VYB www.ti.com 7.2.7 SNLS266D – MAY 2007 – REVISED APRIL 2013 Descrambler A serial descrambler is used to de-scramble the received NRZ data.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 7.3 www.ti.com 10BASE-T TRANSCEIVER MODULE The 10BASE-T Transceiver Module is IEEE 802.3 compliant. It includes the receiver, transmitter, collision, heartbeat, loopback, jabber, and link integrity functions, as defined in the standard. An external filter is not required on the 10BASE-T interface since this is integrated inside the DP83848VYB. This section focuses on the general 10BASE-T system level operation. 7.3.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Figure 7-5. 10BASE-T Twisted Pair Smart Squelch Operation 7.3.3 Collision Detection and SQE When in Half Duplex, a 10BASE-T collision is detected when the receive and transmit channels are active simultaneously. Collisions are reported by the COL signal on the MII. Collisions are also reported when a jabber condition is detected. The COL signal remains set for the duration of the collision.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com Once disabled by the Jabber function, the transmitter stays disabled for the entire time that the ENDEC module's internal transmit enable is asserted. This signal has to be de-asserted for approximately 500 ms (the “unjab” time) before the Jabber function re-enables the transmit outputs. The Jabber function is only relevant in 10BASE-T mode. 7.3.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 8 Reset Operation The DP83848VYB includes an internal power-on reset (POR) function and does not need to be explicitly reset for normal operation after power up. If required during normal operation, the device can be reset by a hardware or software reset. 8.1 HARDWARE RESET A hardware reset is accomplished by applying a low pulse (TTL level), with a duration of at least 1 µs, to the RESET_N pin.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 9 Design Guidelines 9.1 TPI NETWORK CIRCUIT Figure 9-1 shows the recommended circuit for a 10/100 Mb/s twisted pair interface. To the right is a partial list of recommended transformers. It is important that the user realize that variations with PCB and component characteristics requires that the application be tested to ensure that the circuit meets the requirements of the intended application.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Crystal A 25 MHz, parallel, 20 pF load crystal resonator should be used if a crystal source is desired. Figure 9-3 shows a typical connection for a crystal resonator circuit. The load capacitor values will vary with the crystal vendors; check with the vendor for the recommended loads. The oscillator circuit is designed to drive a parallel resonance AT cut crystal with a minimum drive level of 100mW and a maximum of 500 µW.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com Table 9-1.
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DP83848VYB www.ti.com 9.4 SNLS266D – MAY 2007 – REVISED APRIL 2013 POWER FEEDBACK CIRCUIT To ensure correct operation for the DP83848VYB, parallel caps with values of 10 µF and 0.1 µF should be placed close to pin 23 (PFBOUT) of the device. Pin 18(PFBIN1), pin 37 (PFBIN2), pin 23 (PFBIN3) and pin 54 (PFBIN4) must be connected to pin 31 (PFBOUT), each pin requires a small capacitor (.1 µF). See Figure 9-3 below for proper connections. Figure 9-3. Power Feedback Connection 9.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 9.6 www.ti.com ENERGY DETECT MODE When Energy Detect is enabled and there is no activity on the cable, the DP83848VYB will remain in a low power mode while monitoring the transmission line. Activity on the line will cause the DP83848VYB to go through a normal power up sequence. Regardless of cable activity, the DP83848VYB will occasionally wake up the transmitter to put ED pulses on the line, but will otherwise draw as little power as possible.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 10 Register Block 10.1 Register Block Table 10-1.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com Table 10-2.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Table 10-2.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 10.1.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Table 10-3. Basic Mode Control Register (BMCR), address 0x00h (continued) Bit Bit Name Default 9 RESTART AUTO-NEGOTIATION 0, RW/SC DUPLEX MODE Strap, RW Description Restart Auto-Negotiation: 1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation process. If AutoNegotiation is disabled (bit 12 = 0), this bit is ignored.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com Table 10-4. Basic Mode Status Register (BMSR), address 0x01h (continued) Bit Bit Name Default 2 LINK STATUS 0, RO/LL Description Link Status: 1 = Valid link established (for either 10 or 100 Mb/s operation). 0 = Link not established. The criteria for link validity is implementation specific. The occurrence of a link failure condition will causes the Link Status bit to clear.
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DP83848VYB www.ti.com 10.1.1.5 SNLS266D – MAY 2007 – REVISED APRIL 2013 Auto-Negotiation Advertisement Register (ANAR) This register contains the advertised abilities of this device as they will be transmitted to its link partner during Auto-Negotiation. Table 10-7. Negotiation Advertisement Register (ANAR), address 0x04h Bit Bit Name Default 15 NP 0, RW Description Next Page Indication: 0 = Next Page Transfer not desired. 1 = Next Page Transfer desired.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com Table 10-7. Negotiation Advertisement Register (ANAR), address 0x04h (continued) Bit Bit Name Default 7 TX Strap, RW Description 100BASE-TX Support: 1 = 100BASE-TX is supported by the local device. 0 = 100BASE-TX not supported. 6 10_FD Strap, RW 10BASE-T Full Duplex Support: 1 = 10BASE-T Full Duplex is supported by the local device. 0 = 10BASE-T Full Duplex not supported.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Table 10-8. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05h (continued) Bit Bit Name Default 7 TX 0, RO Description 100BASE-TX Support: 1 = 100BASE-TX is supported by the Link Partner. 0 = 100BASE-TX not supported by the Link Partner. 6 10_FD 0, RO 10BASE-T Full Duplex Support: 1 = 10BASE-T Full Duplex is supported by the Link Partner. 0 = 10BASE-T Full Duplex not supported by the Link Partner.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 10.1.1.8 Auto-Negotiate Expansion Register (ANER) This register contains additional Local Device and Link Partner status information. Table 10-10. Auto-Negotiate Expansion Register (ANER), address 0x06h Bit Bit Name Default 15:5 RESERVED 0, RO RESERVED: Writes ignored, Read as 0. Description 4 PDF 0, RO Parallel Detection Fault: 1 = A fault has been detected via the Parallel Detection function. 0 = A fault has not been detected.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Table 10-11. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07h (continued) Bit Bit Name 10:0 CODE Default Description <000 0000 0001>, RW Code: This field represents the code field of the next page transmission. If the MP bit is set (bit 13 of this register), then the code shall be interpreted as a "Message Page”, as defined in annex 28C of IEEE 802.3u.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com Table 10-12. PHY Status Register (PHYSTS), address 10h (continued) Bit Bit Name Default 8 PAGE RECEIVED 0, RO Description Link Code Word Page Received: This is a duplicate of the Page Received bit in the ANER register, but this bit will not be cleared upon a read of the PHYSTS register. 1 = A new Link Code Word Page has been received. Cleared on read of the ANER (address 06h, bit 1). 0 = Link Code Word Page has not been received.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 10.1.2.2 MII Interrupt Control Register (MICR) This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Energy Detect State Change, Link State Change, Speed Status Change, Duplex Status Change, Auto-Negotiation Complete or any of the counters becoming half-full.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com Table 10-14. MII Interrupt Status and Misc. Control Register (MISR), address 0x12h (continued) Bit Bit Name Default 10 ANC_INT 0, RO/COR Description Auto-Negotiation Complete interrupt: 1 = Auto-negotiation complete interrupt is pending and is cleared by the current read. 0 = No Auto-negotiation complete interrupt pending.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 10.1.2.6 100 Mb/s PCS Configuration and Status Register (PCSR) This register contains control and status information for the 100BASE Physical Coding Sublayer. Table 10-17. 100 Mb/s PCS Configuration and Status Register (PCSR), address 0x16h Bit Bit Name Default 15:13 RESERVED <00>, RO Description 12 RESERVED 0 11 FREE_CLK 0, RW Receive Clock: 10 TQ_EN 0, RW 100Mbs True Quiet Mode Enable: RESERVED: Writes ignored, read as 0.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 10.1.2.7 RMII and Bypass Register (RBR) This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed. Table 10-18. RMII and Bypass Register (RBR), addresses 0x17h Bit Bit Name Default 15:6 RESERVED 0, RO 5 RMII_MODE Strap, RW Description RESERVED: Writes ignored, read as 0. Reduced MII Mode: 0 = Standard MII Mode. 1 = Reduced MII Mode.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 10.1.2.9 PHY Control Register (PHYCR) This register provides control for Phy functions such as MDIX, BIST, LED configuration, and Phy address. It also provides Pause Negotiation status. Table 10-20. PHY Control Register (PHYCR), address 0x19h Bit Bit Name Default 15 MDIX_EN Strap, RW Description Auto-MDIX Enable: 1 = Enable Auto-neg Auto-MDIX capability. 0 = Disable Auto-neg Auto-MDIX capability.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com Table 10-20.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Table 10-21. 10Base-T Status/Control Register (10BTSCR), address 1Ah (continued) Bit Bit Name Default 3 RESERVED 0, RW RESERVED: Must be zero. Description 2 RESERVED 1, RW RESERVED: Must be set to one. 1 HEARTBEAT_DIS 0, RW Heartbeat Disable: This bit only has influence in half-duplex 10Mb mode. 1 = Heartbeat function disabled. 0 = Heartbeat function enabled.
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DP83848VYB SNLS266D – MAY 2007 – REVISED APRIL 2013 www.ti.com 10.1.2.12 Energy Detect Control (EDCR) This register provides control and status for the Energy Detect function. Table 10-23. Energy Detect Control (EDCR), address 0x1Dh Bit Bit Name Default 15 ED_EN 0, RW Description Energy Detect Enable: Allow Energy Detect Mode. When Energy Detect is enabled and Auto-Negotiation is disabled via the BMCR register, Auto-MDIX should be disabled via the PHYCR register.
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DP83848VYB www.ti.com SNLS266D – MAY 2007 – REVISED APRIL 2013 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April 2013) to Revision D • Changed layout of National Data Sheet to TI format Page ..........................................................................
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PACKAGE OPTION ADDENDUM www.ti.com 24-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) DP83848VYB/NOPB ACTIVE Package Type Package Pins Package Drawing Qty HLQFP PTB 48 250 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR Op Temp (°C) Device Marking (4/5) -40 to 105 DP83848 VYB (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.