Datasheet

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DP83848T
7.2.5 RMII and Bypass Register (RBR)
This register configures the RMII Mode of operation. When RMII mode is disabled, the RMII functionality is bypassed.
Table 25. RMII and Bypass Register (RBR), addresses 0x17
Bit Bit Name Default Description
15:6 RESERVED 0, RO RESERVED: Writes ignored, Read as 0.
5 RMII_MODE
Strap, RW
Reduced MII Mode:
0 = Standard MII Mode
1 = Reduced MII Mode
4 RMII_REV1_0
0, RW
Reduce MII Revision 1.0:
0 = (RMII revision 1.2) CRS_DV will toggle at the end of a packet
to indicate deassertion of CRS.
1 = (RMII revision 1.0) CRS_DV will remain asserted until final data
is transferred. CRS_DV will not toggle at the end of a packet.
3 RX_OVF_STS
0, RO
RX FIFO Over Flow Status:
0 = Normal
1 = Overflow detected
2 RX_UNF_STS
0,RO
RX FIFO Under Flow Status:
0 = Normal
1 = Underflow detected
1:0 ELAST_BUF[1:0] 1, RW Receive Elasticity Buffer. This field controls the Receive Elastic-
ity Buffer which allows for frequency variation tolerance between
the 50MHz RMII clock and the recovered data. The following value
indicate the tolerance in bits for a single packet. The minimum set-
ting allows for standard Ethernet frame sizes at +/-50ppm accuracy
for both RMII and Receive clocks. For greater frequency tolerance
the packet lengths may be scaled (i.e. for +/-100ppm, the packet
lengths need to be divided by 2).
00 = 14 bit tolerance (up to 16800 byte packets)
01 = 2 bit tolerance (up to 2400 byte packets)
10 = 6 bit tolerance (up to 7200 byte packets)
11 = 10 bit tolerance (up to 12000 byte packets)