Datasheet

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DP83848M
4.0 Architecture
This section describes the operations within each trans-
ceiver module, 100BASE-TX and 10BASE-T. Each opera-
tion consists of several functional blocks and described in
the following:
— 100BASE-TX Transmitter
— 100BASE-TX Receiver
— 10BASE-T Transceiver Module
4.1 100BASE-TX TRANSMITTER
The 100BASE-TX transmitter consists of several func-
tional blocks which convert synchronous 4-bit nibble data,
as provided by the MII, to a scrambled MLT-3 125 Mb/s
serial data stream. Because the 100BASE-TX TP-PMD is
integrated, the differential output pins, PMD Output Pair,
can be directly routed to the magnetics.
The block diagram in Figure 6. provides an overview of
each functional block within the 100BASE-TX transmit
section.
The Transmitter section consists of the following func-
tional blocks:
— Code-group Encoder and Injection block
— Scrambler block (bypass option)
— NRZ to NRZI encoder block
— Binary to MLT-3 converter / Common Driver
The bypass option for the functional blocks within the
100BASE-TX transmitter provides flexibility for applica-
tions where data conversion is not always required. The
DP83848M implements the 100BASE-TX transmit state
machine diagram as specified in the IEEE 802.3u Stan-
dard, Clause 24.
Figure 6. 100BASE-TX Transmit Block Diagram
4B5B CODE-GROUP
ENCODER &
INJECTOR
SCRAMBLER
NRZ TO NRZI
ENCODER
5B PARALLEL
TO SERIAL
PMD OUTPUT PAIR
TX_CLK TXD[3:0] /
TX_EN
BINARY
TO MLT-3 /
COMMON
DRIVER
125MHZ CLOCK
BP_SCR
MUX
100BASE-TX
LOOPBACK
MLT[1:0]
DIVIDE
BY 5