Datasheet

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DP83847

1.2 10 Mb/s and 100 Mb/s PMD Interface

RXD[3]

RXD[2]

RXD[1]

RXD[0]

O, PU/PD 26, 27, 29,

RECEIVE DATA: Nibble wide receive data (synchronous to cor-

responding RX_CLK, 25 MHz for 100BASE-TX mode, 2.5 MHz

for 10BASE-T nibble mode). Data is driven on the falling edge of

RX_CLK. RXD[2] has an internal pull-down resistor. The remain-

ing RXD pins have pull-ups.

RX_ER/PAUSE_EN

S, O, PU 33 RECEIVE ERROR: Asserted high to indicate that an invalid sym-

bol has been detected within a received packet in 100BASE-TX

mode.

RX_DV O 31 RECEIVE DATA VALID: Asserted high to indicate that valid data

is present on the corresponding RXD[3:0] for nibble mode. Data

is driven on the falling edge of the corresponding RX_CLK.

Signal Name Type LLP Pin # Description

TD+, TD- O 10, 11 Differential common driver transmit output. These differential out-

puts are configurable to either 10BASE-T or 100BASE-TX signal-

ing.

The DP83847 will automatically configure the common driver out-

puts for the proper signal type as a result of either forced config-

uration or Auto-Negotiation.

RD-, RD+ I 6, 7 Differential receive input. These differential inputs can be config-

ured to accept either 100BASE-TX or 10BASE-T signaling.

The DP83847 will automatically configure the receive inputs to

accept the proper signal type as a result of either forced configu-

ration or Auto-Negotiation.