Datasheet

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DP83847
given PHYAD input is resistively pulled high, then the cor-
responding output will be configured as an active low
driver. Refer to Figure 1 for an example of a PHYAD con-
nection to external components. In this example, the
PHYAD strapping results in address 00011 (03h).
The adaptive nature of the LED outputs helps to simplify
potential implementation issues of these dual purpose pins.
2.3 LED INTERFACES
The DP83847 has 6 Light Emitting Diode (LED) outputs,
each capable to drive a maximum of 10 mA, to indicate the
status of Link, Transmit, Receive, Collision, Speed, and
Full/Half Duplex operation. The LED_CFG strap option is
used to configure the LED_FDPLX output for use as an
LED driver or more general purpose control pin. See the
table below:
The LED_FDPLX pin indicates the Half or Full Duplex con-
figuration of the port in both 10 Mb/s and 100 Mb/s opera-
tion. Since this pin is also used as the PHY address strap
option, the polarity of this indicator may be adjusted so that
in the “active” (FULL DUPLEX selected) state it drives
against the pullup/pulldown strap. In this configuration it is
suitable for use as an LED. When LED_CFG is high this
mode is selected and DsPHYTER automatically adjusts the
polarity of the output. If LED_CFG is low, the output drives
high to indicate the “active” state. In this configuration the
output is suitable for use as a control pin. The
LED_SPEED pin indicates 10 or 100 Mb/s data rate of the
port. The standard CMOS driver goes high when operating
in 100 Mb/s operation. Since this pin is not utilized as a
strap option, it is not affected by polarity adjustment.
The LED_GDLNK pin indicates the link status of the port.
Since this pin is also used as the PHY address strap
option, the polarity of this indicator is adjusted to be the
inverse of the strap value.
In 100BASE-T mode, link is established as a result of input
receive amplitude compliant with TP-PMD specifications
which will result in internal generation of signal detect.
10 Mb/s Link is established as a result of the reception of at
least seven consecutive normal Link Pulses or the recep-
tion of a valid 10BASE-T packet. This will cause the asser-
tion of GD_LINK. GD_LINK will deassert in accordance
with the Link Loss Timer as specified in IEEE 802.3.
The Collision LED indicates the presence of collision activ-
ity for 10 Mb/s or 100 Mb/s Half Duplex operation. This bit
has no meaning in Full Duplex operation and will be deas-
serted when the port is operating in Full Duplex. Since this
pin is also used as the PHY address strap option, the
polarity of this indicator is adjusted to be the inverse of the
strap value. In 10 Mb/s half duplex mode, the collision LED
is based on the COL signal. When in this mode, the user
should disable the Heartbeat (SQE) to avoid asserting the
COL LED during transmission. See Section 3.4.2 for more
information about the Heartbeat signal.
The LED_RX and LED_TX pins indicate the presence of
transmit and/or receive activity. Since these pins are also
used in PHY address strap options, the polarity is adjusted
to be the inverse of the respective strap values.
2.4 Half Duplex vs. Full Duplex
The DP83847 supports both half and full duplex operation
at both 10 Mb/s and 100 Mb/s speeds.
Half-duplex is the standard, traditional mode of operation
which relies on the CSMA/CD protocol to handle collisions
and network access. In Half-Duplex mode, CRS responds
to both transmit and receive activity in order to maintain
compliance with IEEE 802.3 specification.
Since the DP83847 is designed to support simultaneous
transmit and receive activity it is capable of supporting full-
Figure 1. PHYAD Strapping and LED Loading Example
LED_FDPLX LED_COL LED_GDLNK
LED_TX
LED_RX
VCC
10kΩ
1kΩ
1kΩ
10kΩ
1kΩ
10kΩ
1kΩ
10kΩ
1kΩ
PHYAD0 = 1
PHYAD1 = 1
PHYAD2 = 0PHYAD3 = 0
PHYAD4= 0
10kΩ
Table 3. LED Mode Select
LED_CFG Mode Description
1 LED polarity adjusted
0 Duplex active-high