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DP83847

DP83847 DsPHYTER II - Single 10/100 Ethernet Transceiver

Literature Number: SNLS157

Summary of content (62 pages)

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DP83847 DP83847 DsPHYTER II - Single 10/100 Ethernet Transceiver Literature Number: SNLS157
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DP83847 DsPHYTER II — Single 10/100 Ethernet Transceiver General Description Features The DP83847 is a full feature single Physical Layer device ■ Low-power 3.3V, 0.18µm CMOS technology with integrated PMD sublayers to support both 10BASE-T ■ Power consumption < 351mW (typical) and 100BASE-TX Ethernet protocols over Category 3 (10 ■ 5V tolerant I/Os Mb/s) or Category 5 unshielded twisted pair cables. ■ 5V/3.
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DP83847 RX_CLK RXD[3:0] RX_DV RX_ER CRS COL MDC MDIO TX_EN SERIAL MANAGEMENT TX_ER TX_CLK HARDWARE CONFIGURATION PINS (AN_EN, AN0, AN1) (PAUSE_EN) (LED_CFG, PHYAD) TXD[3:0] MII MII INTERFACE/CONTROL RX_DATA RX_CLK TX_DATA TX_DATA TRANSMIT CHANNELS & STATE MACHINES 100 Mb/s 4B/5B ENCODER PARALLEL TO SERIAL SCRAMBLER 10 Mb/s LINK PULSE GENERATOR NRZ TO NRZI ENCODER BINARY TO MLT-3 ENCODER RX_CLK TX_CLK REGISTERS MII PHY ADDRESS NRZ TO MANCHESTER ENCODER RX_DATA RECEIVE CHANNELS & STAT
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DP83847 Table of Content 1.0 2.0 3.0 4.0 5.0 6.0 7.0 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 MII Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 10 Mb/s and 100 Mb/s PMD Interface . . . . . . . . . . 6 1.3 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.4 Special Connections . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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DP83847 62 59 60 65 Gnd 64 58 63 28 VDD 27 RXD_2 26 RXD_3 25 MDC 24 MDIO 23 LED_DPLX/PHYAD0 22 LED_COL/PHYAD1 21 LED_GDLNK/PHYAD2 20 LED_TX/PHYAD3 19 LED_RX/PHYAD4 18 LED_SPEED 17 AN_EN 16 AN_1 15 AN_0 RESERVED 1 RESERVED 2 RBIAS 3 RESERVED 4 RESERVED 5 RD - 6 RD+ 7 RESERVED 8 RESERVED 9 TD+ 10 TD- 11 RESERVED 12 RESERVED 13 VDD 14 57 COL 43 RESERVED 44 CRS/LED_CFG 45 RESET 46 RESERVED 47 X2 48 X1 49 RESERVED 50 RESERVED 51 RESERVED 52 RESERVED 53 RESERVED 54 RESERVED 55 VDD 56 61 42 C1 41 TXD_3
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The DP83847 pins are classified into the following interface categories (each interface is described in the sections that follow): All DP83847 signal pins are I/O cells regardless of the particular use. Below definitions define the functionality of the I/O cells for each pin. — MII Interface — 10/100 Mb/s PMD Interface — Clock Interface — Special Connect Pins — LED Interface — Strapping Options/Dual Function pins — Reset — Power and Ground pins Note: Strapping pin option (BOLD) Please see Section 1.
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RXD[3] Type LLP Pin # Description RXD[2] RXD[1] RXD[0] O, PU/PD 26, 27, 29, RECEIVE DATA: Nibble wide receive data (synchronous to cor30 responding RX_CLK, 25 MHz for 100BASE-TX mode, 2.5 MHz for 10BASE-T nibble mode). Data is driven on the falling edge of RX_CLK. RXD[2] has an internal pull-down resistor. The remaining RXD pins have pull-ups. RX_ER/PAUSE_EN S, O, PU 33 RECEIVE ERROR: Asserted high to indicate that an invalid symbol has been detected within a received packet in 100BASE-TX mode.
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DP83847 1.3 Clock Interface Signal Name Type LLP Pin # Description X1 I 49 REFERENCE CLOCK INPUT 25 MHz: This pin is the primary clock reference input for the DP83847 and must be connected to a 25 MHz 0.005% (±50 ppm) clock source. The DP83847 supports CMOS-level oscillator sources. X2 O 48 REFERENCE CLOCK OUTPUT 25 MHz: This pin is the primary clock reference output. 1.4 Special Connections Type LLP Pin # Description RBIAS Signal Name I 3 Bias Resistor Connection. A 10.
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tors will set the default value. Please note that the PHYAD[0:4] pins have no internal pull-ups or pull-downs A 5 kΩ resistor should be used for pull-down or pull-up to and they must be strapped. Since these pins may have change the default strap option. If the default option is alternate functions after reset is deasserted, they should required, then there is no need for external pull-up or pull not be connected directly to Vcc or GND.
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RX_ER/PAUSE_EN Type LLP Pin # Description S, O, PU 33 PAUSE ENABLE: This strapping option allows advertisement of whether or not the DTE(MAC) has implemented both the optional MAC control sublayer and the pause function as specified in clause 31 and annex 31B of the IEEE 802.3x specification (Full Duplex Flow Control). When left floating the Auto-Negotiation Advertisement Register will be set to 0, indicating that Full Duplex Flow Control is not supported.
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LLP Pin # LLP Pin # Pin Name 1 RESERVED 2 RESERVED 3 RBIAS 4 RESERVED 5 RESERVED 6 RD- 7 RD+ 8 RESERVED 9 RESERVED 10 TD+ 11 TD- 12 RESERVED 13 RESERVED 14 VDD (ANA_VDD) 15 AN_0 16 AN_1 17 AN_EN 18 LED_SPEED 19 LED_RX /PHYAD4 20 LED_TX /PHYAD3 21 LED_GDLNK/PHYAD2 22 LED_COL /PHYAD1 23 LED_FDPLX /PHYAD0 24 MDIO 25 MDC 26 RXD_3 27 RXD_2 28 VDD (IO_VDD) 29 RXD_1 30 RXD_0 31 RX_DV 32 RX_CLK 33 RX_ER/PAUSE_EN 34 RESERVED 35 TX_ER 36 TX_CLK
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This section includes information on the various configuration options available with the DP83847. The configuration options described below include: — — — — — — Table 1. Auto-Negotiation Modes Auto-Negotiation PHY Address and LEDs Half Duplex vs. Full Duplex Isolate mode Loopback mode BIST AN_EN AN1 AN0 0 0 0 10BASE-T, Half-Duplex Forced Mode 0 0 1 10BASE-T, Full-Duplex 0 1 0 100BASE-TX, Half-Duplex 100BASE-TX, Full-Duplex 0 1 1 AN_EN AN1 AN0 1 0 0 10BASE-T, Half/Full-Duplex 2.
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— Whether Auto-Negotiation is complete — Whether the Link Partner is advertising that a remote fault has occurred — Whether valid link has been established — Support for Management Frame Preamble suppression The Auto-Negotiation Advertisement Register (ANAR) indicates the Auto-Negotiation abilities to be advertised by the DP83847. All available abilities are transmitted by default, but any ability can be suppressed by writing to the ANAR.
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LED_FDPLX LED_COL LED_GDLNK LED_TX LED_RX 1kΩ 10kΩ 1kΩ 10kΩ 1kΩ 10kΩ 1kΩ 10kΩ 1kΩ 10kΩ PHYAD4= 0 PHYAD3 = 0 PHYAD2 = 0 PHYAD1 = 1 PHYAD0 = 1 VCC Figure 1. PHYAD Strapping and LED Loading Example 2.3 LED INTERFACES The DP83847 has 6 Light Emitting Diode (LED) outputs, each capable to drive a maximum of 10 mA, to indicate the status of Link, Transmit, Receive, Collision, Speed, and Full/Half Duplex operation.
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2.6 Loopback The DP83847 includes a Loopback Test mode for facilitating system diagnostics. The Loopback mode is selected through bit 14 (Loopback) of the Basic Mode Control Register (BMCR). Writing 1 to this bit enables MII transmit data to be routed to the MII receive outputs. Loopback status may be checked in bit 3 of the PHY Status Register (PHYSTS). While in Loopback mode the data will not be All modes of operation (100BASE-TX and 10BASE-T) can transmitted onto the media in 100 Mb/s mode.
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3.1 802.3u MII mat is shown below in Table 4: Typical MDIO Frame Format. The DP83847 incorporates the Media Independent Interface (MII) as specified in Clause 22 of the IEEE 802.3u standard. This interface may be used to connect PHY devices to a MAC in 10/100 Mb/s systems. This section describes both the serial MII management interface as well as the nibble wide MII data interface. The MDIO pin requires a pull-up resistor (1.5 kΩ) which, during IDLE and turnaround, will pull MDIO high.
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MDIO Z Z (STA) Z Idle 0 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Start Opcode (Write) PHY Address (PHYAD = 0Ch) Register Address (00h = BMCR) Register Data TA Z Idle Figure 3. Typical MDC/MDIO Write Operation returning a one in this bit, then the station management 3.1.6 Collision Detect entity need not generate preamble for each management For Half Duplex, a 10BASE-T or 100BASE-TX collision is transaction.
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TX_CLK TXD[3:0] / TX_ER DIV BY 5 FROM PGM 4B5B CODEGROUP ENCODER & INJECTOR MUX BP_4B5B 5B PARALLEL TO SERIAL SCRAMBLER MUX BP_SCR NRZ TO NRZI ENCODER 100BASE-TX LOOPBACK BINARY TO MLT-3 / COMMON DRIVER TD± Figure 4. 100BASE-TX Transmit Block Diagram 3.2.
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3.2.3 NRZ to NRZI Encoder After the transmit data stream has been serialized and scrambled, the data must be NRZI encoded in order to comply with the TP-PMD standard for 100BASE-TX transmission over Category-5 Unsheilded twisted pair cable. 3.2.4 Binary to MLT-3 Convertor / Common Driver The Binary to MLT-3 conversion is accomplished by converting the serial binary data stream output from the NRZI encoder into two binary data streams with alternately phased logic one events.
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DP83847 Table 5.
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The 100BASE-TX transmit TP-PMD function within the DP83847 is capable of sourcing only MLT-3 encoded data. Binary output from the TD± outputs is not possible in 100 Mb/s mode. 3.3 100BASE-TX RECEIVER The 100BASE-TX receiver consists of several functional blocks which convert the scrambled MLT-3 125 Mb/s serial data stream to synchronous 4-bit nibble data that is provided to the MII.
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DP83847 RX_CLK RXD[3:0] / RX_ER ÷5 MUX BP_4B5B 4B/5B DECODER SERIAL TO PARALLEL CODE GROUP ALIGNMENT BP_SCR MUX DESCRAMBLER CLOCK CLOCK RECOVERY MODULE NRZI TO NRZ DECODER LINK STATUS MLT-3 TO BINARY DECODER DIGITAL ADAPTIVE EQUALIZATION AGC LINK MONITOR SIGNAL DETECT INPUT BLW COMPENSATION ADC RD± Figure 7. Receive Block Diagram 21 www.national.
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The signal detect function of the DP83847 is incorporated to meet the specifications mandated by the ANSI FDDI TPPMD Standard as well as the IEEE 802.3 100BASE-TX Standard for both voltage thresholds and timing parameters. The CRM is implemented using an advanced all digital Phase Locked Loop (PLL) architecture that replaces sensitive analog circuitry. Using digital PLL circuitry allows the DP83847 to be manufactured and specified to tighter tolerances.
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3.4.2 Collision Detection and SQE The code-group decoder functions as a look up table that translates incoming 5B code-groups into 4B nibbles. The code-group decoder first detects the J/K code-group pair preceded by IDLE code-groups and replaces the J/K with MAC preamble. Specifically, the J/K 10-bit code-group pair is replaced by the nibble pair (0101 0101). All subsequent 5B code-groups are converted to the corresponding 4B nibbles for the duration of the entire packet.
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Transmission ends when TX_EN deasserts. The last transition is always positive; it occurs at the center of the bit cell if the last bit is a one, or at the end of the bit cell if the last bit is a zero. The inverse polarity condition is latched in the 10BTSCR register. The DP83847's 10BASE-T transceiver module corrects for this error internally and will continue to decode 3.4.9 Receiver received data correctly.
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Typically, ESD precautions are predominantly in effect when handling the devices or board before being installed in a system. In those cases, strict handling procedures can be implemented during the manufacturing process to greatly reduce the occurrences of catastrophic ESD events. After the system is assembled, internal components are usually relatively immune from ESD events.
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3.8 Reference Bypass Couple The DsPHYTER II supports an external CMOS level oscillator source or a crystal resonator device. If an external clock source is used, X1 should be tied to the clock source and X2 should be left floating. In either case, the clock source must be a 25 MHz 0.005% (50 PPM) CMOS oscillator or a 25 MHz (50 PPM), parallel, 20 pF load crystal resonator. Figure 10 below shows a typical connection for a crystal resonator circuit.
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DP83847 5.0 Register Block Table 6.
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Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Basic Mode Control Register Register Name 00h Addr BMCR Tag Reset Loopback Speed Select Auto-Neg Enable Power down Isolate Restart Auto-Neg Duplex Collision Test Reserved Reserved Reserved Reserved Reserved Reserved Reserved Basic Mode Status Register 01h BMSR 100BaseT4 100BaseTX FDX 100BaseTX HDX 10BaseT FDX 10BaseT HDX Reserved Reserved Reserved Reserved MF Pre
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DP83847 5.
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DP83847 Table 7. Basic Mode Control Register (BMCR), Address 0x00 Bit Bit Name 15 Reset Default Description 0, RW/SC Reset: 1 = Initiate software Reset / Reset in Process. 0 = Normal operation. This bit, which is self-clearing, returns a value of one until the reset process is complete. The configuration is re-strapped. 14 Loopback 0, RW Loopback: 1 = Loopback enabled. 0 = Normal operation. The loopback function enables MII transmit data to be routed to the MII receive data path.
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DP83847 Table 8. Basic Mode Status Register (BMSR), address 0x01 Bit Bit Name Default 15 100BASE-T4 0, RO/P Description 100BASE-T4 Capable: 0 = Device not able to perform 100BASE-T4 mode. 14 100BASE-TX 1, RO/P Full Duplex 13 100BASE-TX 1 = Device able to perform 100BASE-TX in full duplex mode. 1, RO/P Half Duplex 12 10BASE-T 10BASE-T 100BASE-TX Half Duplex Capable: 1 = Device able to perform 100BASE-TX in half duplex mode.
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Table 9. PHY Identifier Register #1 (PHYIDR1), address 0x02 Bit Bit Name 15:0 OUI_MSB Bit Bit Name 15:10 OUI_LSB Default Description <0010 0000 0000 OUI Most Significant Bits: Bits 3 to 18 of the OUI (080017h) are 0000>, RO/P stored in bits 15 to 0 of this register. The most significant two bits of the OUI are ignored (the IEEE standard refers to these as bits 1 and 2). Table 10.
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Table 11. Auto-Negotiation Advertisement Register (ANAR), address 0x04 Bit Bit Name Default 15 NP 0, RW Description Next Page Indication: 0 = Next Page Transfer not desired. 1 = Next Page Transfer desired. 14 RESERVED 0, RO/P 13 RF 0, RW RESERVED by IEEE: Writes ignored, Read as 0. Remote Fault: 1 = Advertises that this device has detected a Remote Fault. 0 = No Remote Fault detected.
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Table 12. Auto-Negotiation Link Partner Ability Register (ANLPAR) (BASE Page), address 0x05 Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 0 = Link Partner does not desire Next Page Transfer. 1 = Link Partner desires Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged. The Device's Auto-Negotiation state machine will automatically control the this bit based on the incoming FLP bursts.
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Bit Bit Name Default 15 NP 0, RO Description Next Page Indication: 1 = Link Partner desires Next Page Transfer. 0 = Link Partner does not desire Next Page Transfer. 14 ACK 0, RO Acknowledge: 1 = Link Partner acknowledges reception of the ability data word. 0 = Not acknowledged. The Device's Auto-Negotiation state machine will automatically control the this bit based on the incoming FLP bursts. Software should not attempt to write to this bit. 13 MP 0, RO Message Page: 1 = Message Page.
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Table 15. Auto-Negotiation Next Page Transmit Register (ANNPTR), address 0x07 Bit Bit Name Default 15 NP 0, RW Description Next Page Indication: 0 = No other Next Page Transfer desired. 1 = Another Next Page desired. 14 RESERVED 0, RO RESERVED: Writes ignored, read as 0. 13 MP 1, RW Message Page: 1 = Message Page. 0 = Unformatted Page. 12 ACK2 0, RW Acknowledge2: 1 = Will comply with message. 0 = Cannot comply with message.
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This register provides a single location within the register set for quick access to commonly accessed information. Table 16. PHY Status Register (PHYSTS), address 0x10 Bit Bit Name Default 15:14 RESERVED 0, RO 13 Receive Error Latch 0, RO/LH Description RESERVED: Write ignored, read as 0. Receive Error Latch: This bit will be cleared upon a read of the RECR register. 1 = Receive error event has occurred since last read of RXERCNT (address 0x15, Page 0). 0 = No receive error event has occurred.
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DP83847 Table 16. PHY Status Register (PHYSTS), address 0x10 (Continued) Bit Bit Name Default Description 7 RESERVED 0, RO RESERVED: Writes ignored, Read as 0. 6 Remote Fault 0, RO Remote Fault: 1 = Remote Fault condition detected (cleared on read of BMSR (address 01h) register or by reset). Fault criteria: notification from Link Partner of Remote Fault via Auto-Negotiation. 0 = No remote fault condition detected.
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Table 18. Receiver Error Counter Register (RECR), address 0x15 Bit Bit Name Default 15:8 RESERVED 0, RO 7:0 RXERCNT[7:0] 0, RW / COR Description RESERVED: Writes ignored, Read as 0 RX_ER Counter: This 8-bit counter increments for each receive error detected. When a valid carrier is present and there is at least one occurrence of an invalid data symbol. This event can increment only once per valid carrier event. If a collision is present, the attribute will not increment.
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Bit Bit Name Default 7 Unused 0,RO 6 RESERVED 0 Description RESERVED: Must be zero. 5 FORCE_100_OK 0, RW Force 100Mb/s Good Link: 1 = Forces 100Mb/s Good Link. 0 = Normal 100Mb/s operation. 4 RESERVED 0 RESERVED: Must be zero. 3 RESERVED 0 2 NRZI_BYPASS 0, RW RESERVED: Must be zero. NRZI Bypass Enable: 1 = NRZI Bypass Enabled. 0 = NRZI Bypass Disabled. 1 SCRAM_BYPASS 0, RW Scrambler Bypass Enable: 1 = Scrambler Bypass Enabled. 0 = Scrambler Bypass Disabled.
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DP83847 Table 21. PHY Control Register (PHYCTRL), address 0x19 Bit Bit Name Default 15:12 Unused 0, RO 11 PSR_15 0, RW Description BIST Sequence select: 1 = PSR15 selected. 0 = PSR9 selected. 10 BIST_STATUS 0, RO/LL BIST Test Status: 1 = BIST pass. 0 = BIST fail. Latched, cleared by write to BIST_ START bit. 9 BIST_START 0, RW BIST Start: 1 = BIST start. 0 = BIST stop.
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DP83847 Table 22. 10Base-T Status/Control Register (10BTSCR), Address 0x1A Bit Bit Name Default 15:9 Unused 0, RO 8 LOOPBACK_10_DIS 0, RW Description 10BASE-T Loopback Disable: If bit 14 (Loopback) in the BMCR is 0: 1 = 10 Mb/s Loopback is disabled. If bit 14 (Loopback) in the BMCR is 1: 1 = 10 Mb/s Loopback is enabled. 7 LP_DIS 0, RW Normal Link Pulse Disable: 1 = Transmission of NLPs is disabled. 0 = Transmission of NLPs is enabled.
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DP83847 Table 23. CD Test Register (CDCTRL), Address 0x1B Bit Bit Name Default 15 CD_ENABLE 1, RW Description CD Enable: 1 = CD Enabled - power-down mode, outputs high impedance. 0 = CD Disabled. 14 DCDCOMP 0, RW Duty Cycle Distortion Compensation: 1 = Increases the amount of DCD compensation. 13 FIL_TTL 0, RW Waveshaper Current Source Test: To check ability of waveshaper current sources to switch on/off. 1 = Test mode; waveshaping is done, but the output is a square wave.
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Absolute Maximum Ratings Recommended Operating Conditions Supply voltage (VCC) 3.3 Volts + 0.3V Supply Voltage (VCC) -0.5 V to 4.2 V DC Input Voltage (VIN) -0.5V to 5.5V Ambient Temperature (TA) DC Output Voltage (VOUT) -0.5V to 5.5V Max. die temperature (Tj) Storage Temperature (TSTG) 240 °C ESD Rating (RZAP = 1.5k, CZAP = 120 pF) 2.0 kV TPTD+/- ESD Rating 1.0 kV 150 °C Max case temp -65oC to 150°C Lead Temp.
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Pin Types VTPTD_10 TD+/− 10M Transmit Voltage I CMOS Input Capacitance CIN1 Parameter Conditions Min Typ Max Units 2.2 2.5 2.
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DP83847 6.1 Reset Timing VCC X1 Clock T1.0.1 T1.0.4 HARDWARE RSTN 32 CLOCKS MDC T1.0.2 Latch-In of Hardware Configuration Pins T1.0.3 INPUT OUTPUT Dual Function Pins Become Enabled As Outputs Parameter Description Notes Min Typ Max Units T1.0.1 Post RESET Stabilization time MDIO is pulled high for 32-bit serial manprior to MDC preamble for reg- agement initialization. ister accesses 3 µs T1.0.
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DP83847 6.2 PGM Clock Timing X1 TX_CLK T2.0.1 Parameter T2.0.1 Description Notes Min TX_CLK Duty Cycle Typ 35 Max Units 65 % Max Units 300 ns 6.3 MII Serial Management Timing MDC T3.0.1 T3.0.4 MDIO (output) MDC T3.0.2 MDIO (input) Parameter Description T3.0.3 Valid Data Notes Min T3.0.1 MDC to MDIO (Output) Delay Time 0 T3.0.2 MDIO (Input) to MDC Setup Time 10 T3.0.3 MDIO (Input) to MDC Hold Time 10 T3.0.4 MDC Frequency Typ ns ns 2.5 47 MHz www.national.
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DP83847 6.4 100 Mb/s Timing 6.4.1 100 Mb/s MII Transmit Timing TX_CLK T4.1.2 T4.1.1 TXD[3:0] TX_EN TX_ER Parameter Valid Data Description Notes Min Typ Max Units T4.1.1 TXD[3:0], TX_EN, TX_ER Data Setup to TX_CLK 10 ns T4.1.2 TXD[3:0], TX_EN, TX_ER Data Hold from TX_CLK 5 ns 6.4.2 100 Mb/s MII Receive Timing T4.2.1 RX_CLK T4.2.2 RXD[3:0] RX_DV RX_ER Parameter Valid Data Max Units T4.2.1 RX_CLK Duty Cycle Description Notes 35 65 % T4.2.
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DP83847 6.4.3 100BASE-TX Transmit Packet Latency Timing TX_CLK TX_EN TXD TD± Parameter T4.3.1 T4.3.1 IDLE (J/K) Description DATA Notes Min Typ TX_CLK to TD± Latency Max Units 6.0 bit times Note: Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the first bit of the “J” code group as output from the TD± pins. 6.4.4 100BASE-TX Transmit Packet Deassertion Timing TX_CLK TX_EN TXD T4.4.1 TD± Parameter T4.4.
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DP83847 6.4.5 100BASE-TX Transmit Timing (tR/F & Jitter) T4.5.1 +1 rise 90% 10% TD± 10% +1 fall 90% T4.5.1 -1 fall -1 rise T4.5.1 T4.5.1 T4.5.2 TD± eye pattern Parameter T4.5.1 T4.5.2 T4.5.2 Description Notes Min Typ Max Units 3 4 5 ns 100 Mb/s tR and tF Mismatch 500 ps 100 Mb/s TD± Transmit Jitter 1.4 ns 100 Mb/s TD± tR and tF Note1: Normal Mismatch is the difference between the maximum and minimum of all rise and fall times.
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DP83847 6.4.6 100BASE-TX Receive Packet Latency Timing RD± IDLE Data (J/K) T4.6.1 CRS T4.6.2 RXD[3:0] RX_DV RX_ER/RXD[4] Parameter Description T4.6.1 Carrier Sense ON Delay T4.6.2 Receive Data Latency Notes Min Typ Max Units 17.5 bit times 21 bit times Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense. Note: RD± voltage amplitude is greater than the Signal Detect Turn-On Threshold Value. 6.4.
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DP83847 6.5 10 Mb/s Timing 6.5.1 10 Mb/s MII Transmit Timing TX_CLK T5.1.2 T5.1.1 TXD[3:0] TX_EN Parameter Valid Data Description Notes Min Typ Max Units T5.1.1 TXD[3:0], TX_EN Data Setup to TX_CLK 25 ns T5.1.2 TXD[3:0], TX_EN Data Hold from TX_CLK 5 ns 6.5.2 10 Mb/s MII Receive Timing T5.2.1 RX_CLK T5.2.2 RXD[3:0] RX_DV Parameter Valid Data Max Units T5.2.1 RX_CLK Duty Cycle Description Notes 35 65 % T5.2.2 RX_CLK to RXD[3:0], RX_DV 190 210 ns 52 Min Typ www.
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DP83847 6.5.3 10BASE-T Transmit Timing (Start of Packet) TX_CLK T5.3.1 TX_EN T5.3.2 TXD[0] T5.3.3 TPTD± T5.3.4 Parameter Description Notes Min Typ Max Units T5.3.1 Transmit Enable Setup Time from the Falling Edge of TX_CLK 25 ns T5.3.2 Transmit Data Setup Time from the Falling Edge of TX_CLK 25 ns T5.3.3 Transmit Data Hold Time from the Falling Edge of TX_CLK 5 ns T5.3.4 Transmit Output Delay from the 6.8 bit times Falling Edge of TX_CLK 6.5.
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DP83847 6.5.5 10BASE-T Receive Timing (Start of Packet) 1st SFD bit decoded 1 0 1 TPRD± T5.5.1 CRS T5.5.2 RX_CLK T5.5.4 RXD[0] T5.5.3 RX_DV Parameter Description Notes Min Typ Max Units 1 µs T5.5.1 Carrier Sense Turn On Delay (TPRD± to CRS) T5.5.2 Decoder Acquisition Time 3.6 µs T5.5.3 Receive Data Latency 17.3 bit times T5.5.4 SFD Propagation Delay 10 bit times Note: 10BASE-T receive Data Latency is measured from first bit of preamble on the wire to the assertion of RX_DV. 6.5.
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DP83847 6.5.7 10 Mb/s Heartbeat Timing TXE TXC T5.7.2 T5.7.1 COL Max Units T5.7.1 Parameter CD Heartbeat Delay Description Notes Min 600 Typ 1600 ns T5.7.2 CD Heartbeat Duration 500 1500 ns Max Units 6.5.8 10 Mb/s Jabber Timing TXE T5.8.1 T5.8.2 TPTD± COL Parameter Description Notes Min Typ T5.8.1 Jabber Activation Time 20 150 ms T5.8.2 Jabber Deactivation Time 250 750 ms Max Units 6.5.9 10BASE-T Normal Link Pulse Timing T5.9.2 T5.9.
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DP83847 6.5.10 Auto-Negotiation Fast Link Pulse (FLP) Timing T5.10.2 T5.10.3 T5.10.1 T5.10.1 Fast Link Pulse(s) clock pulse data pulse clock pulse T5.10.6 T5.10.4 T5.10.5 FLP Burst Parameter FLP Burst Description T5.10.1 Clock, Data Pulse Width T5.10.2 Clock Pulse to Clock Pulse Period T5.10.3 Clock Pulse to Data Pulse Period T5.10.4 Number of Pulses in a Burst T5.10.5 Burst Width T5.10.6 FLP Burst to FLP Burst Period Notes Min Typ Max 100 ns 139 µs 55.5 69.
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DP83847 6.6 Loopback Timing 6.6.1 100 Mb/s Internal Loopback Mode TX_CLK TX_EN TXD[3:0] CRS T6.1.1 RX_CLK RX_DV RXD[3:0] Parameter T6.1.1 Description TX_EN to RX_DV Loopback Notes Min 100 Mb/s internal loopback mode Typ Max Units 240 ns Note1: Due to the nature of the descrambler function, all 100BASE-TX Loopback modes will cause an initial “dead-time” of up to 550 µs during which time no data will be present at the receive MII outputs.
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DP83847 6.6.2 10 Mb/s Internal Loopback Mode TX_CLK TX_EN TXD[3:0] CRS T6.2.1 RX_CLK RX_DV RXD[3:0] Parameter T6.2.1 Description TX_EN to RX_DV Loopback Notes Min 10 Mb/s internal loopback mode Typ Max Units 2 µs Note: Measurement is made from the first falling edge of TX_CLK after assertion of TX_EN. 58 www.national.
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DP83847 6.7 Isolation Timing Clear bit 10 of BMCR (return to normal operation from Isolate mode) T7.0.1 H/W or S/W Reset (with PHYAD = 00000) T7.0.2 MODE NORMAL ISOLATE Parameter Description Notes Min Typ Max Units T7.0.1 From software clear of bit 10 in the BMCR register to the transition from Isolate to Normal Mode 100 µs T7.0.2 From Deassertion of S/W or H/W Reset to transition from Isolate to Normal mode 500 µs 59 www.national.
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DP83847 DsPHYTER II — Single 10/100 Ethernet Transceiver 7.0 Physical Dimensions Leadless Leadframe Package (LLP) Order Number DP83847 LQA56A NS Package Number LQA-56A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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