Datasheet

9.0 Electrical Specifications (Continued)
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9.4.9 100BASE-FX Transmit Packet Deassertion Timing
Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of TX_EN to the first bit of the
“T” code group as output from the FXTD± pins. For Symbol mode, because TX_EN has no meaning, Deassertion is measured from the first rising edge of
TX_CLK occurring after the deassertion of a data nibble on the Transmit MII to the last bit (LSB) of that nibble when it deasserts as output from the FXTD±
pins. 1 bit time = 10 ns in 100 Mb/s mode.
9.4.10 100BASE-FX Receive Packet Latency Timing
Note: Carrier Sense On Delay is determined by measuring the time from the first bit of the “J” code group to the assertion of Carrier Sense.
Note: 1 bit time = 10 ns in 100 Mb/s mode.
Parameter Description Notes Min Typ Max Units
T4.9.1 TX_CLK to FXTD+/−
Deassertion
100 Mb/s Normal mode 4.0 bits
100 Mb/s Symbol mode 4.0 bits
Parameter Description Notes Min Typ Max Units
T4.10.1 Carrier Sense On Delay 100 Mb/s Normal mode 17.5 bits
T4.10.2 Receive Data Latency 100 Mb/s Normal mode 19 bits
100 Mb/s Symbol mode 19 bits
TX_CLK
TX_EN
TXD
FXTD+/-
(T/R)DATA IDLE
T4.9.1
CRS
RXD[3:0]
FXRD+/-
RX_DV
RX_ER/RXD[4]
(J/K)
IDLE
DATA
T4.10.2
T4.10.1