Datasheet

9.0 Electrical Specifications (Continued)
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9.4.8 100BASE-FX Transmit Packet Latency Timing
Note: For Normal mode, Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after the assertion of TX_EN to the
first bit of the “j” code group as output from the FXTD± pins. For Symbol mode, because TX_EN has no meaning, Latency is measured from the first rising
edge of TX_CLK occurring after the assertion of a data nibble on the Transmit MII to the first bit (MSB) of that nibble when it first appears at the FXTD±
outputs.
Parameter Description Notes Min Typ Max Units
T4.8.1 TX_CLK to FXTD+/− Latency 100 Mb/s Normal mode 4.0 bits
100 Mb/s Symbol mode 4.0 bits
TX_CLK
TX_EN
TXD
FXTD+/-
(J/K) IDLE DATA
T4.8.1