Datasheet

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8.0 Register Block (Continued)
9 REPEATER Strap, RW Repeater/Node Mode:
1 = Repeater mode
0 = Node mode
In repeater mode the Carrier Sense (CRS) output from the device
is asserted due to receive activity only. In Node mode, and not
configured for full duplex operation, CRS is asserted due to either
receive or transmit activity. In 100 Mb/s operation the CIM moni-
tor is disabled. In Repeater mode HB_DS is enabled (bit 7 regis-
ter 10BTSCR(18h))
This bit is set according to the strap configuration of the REPEAT-
ER pin at power-up/reset.
8:7 LED_TXRX_MODE <00>, RW LED_TX/RX Mode Select:
<11> = LED_RX indicates both RX and TX activity and LED_TX
indicates interrupt. Interrupt signal is active high.
<10> = LED_RX indicates both RX and TX activity and LED_TX
indicates Carrier Integrity Monitor status.Interrupt signal is active
high.
<01> = LED_RX indicates RX activity only and LED_TX indicates
Carrier Integrity Monitor status.
<00> = Normal LED_TX and LED_RX operation.
Note: Using LED_TX to indicate Carrier Integrity Monitor status
is useful for network management purposes in 100BASE-TX
mode. This mode only works if the PHY_Address_2 is strapped
low because the PHYTER does not properly implement the Activ-
ity LED function if LED_RX/PHYAD[2] is strapped high.
6 LED_DUP_MODE 0, RW LED_DUP Mode Select:
1 = LED_FDPOL configured to indicate polarity reversal in
10BASE-T mode, and full duplex in 100BASE-TX mode
0 = LED_FDPOL configured to indicate full duplex in all operating
modes.
5 FX_EN Strap, RW Fiber Mode Enable:
This bit is set by the
FX_EN at power-on/reset or by software after
reset. If this bit is set then the signals FEFI_EN and BP_SCR are
driven internally. When this bit is set, fiber mode enabled, Auto-
Negotiation must be disabled.
1 = Fiber Mode enabled
0 = Fiber Mode disabled
4:0 PHYADDR[4:0] (STRAP), RW PHY Address:
The values of the PHYAD[4:0] pins are latched to this register at
power-up/reset. The first PHY address bit transmitted or received
is the MSB of the address (bit 4). A station management entity
connected to multiple PHY entities must know the appropriate ad-
dress of each PHY. A PHY address of <00000> that is latched in
to the part at power up/reset will cause the Isolate bit of the
BMCR (bit 10, register address 00h) to be set.
After power up/reset the only way to enable or disable isolate
mode is to set or clear the Isolate bit (bit 10) of BMCR (address
00). After power up/reset writing <00000> to bits [4:0] of this reg-
ister will not cause the part to enter isolate mode.
Table 23. PHY Control Register (PHYCTRL) Address 19h (Continued)
Bit Bit Name Default Description