Datasheet

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8.0 Register Block (Continued)
6 LS_SEL 0, RW Low Squelch Select:
Selects between standard 10BASE-T receiver squelch threshold
and a reduced squelch threshold that is useful for longer cable
applications.
1 = Low Squelch Threshold selected
0 = Normal 10BASE-T Squelch Threshold selected
5 AUI_SEL 0, RW AUI Select:
1 = Select AUI interface
0 = Select TPI interface
4 JAB_DS 0, RW Jabber Disable:
Enables or disables the Jabber function when the device is in
10BASE-T Full Duplex or 10BASE-T TREX Loopback mode
(TREX_LBEN bit 4 in the LBR, address 17h).
1 = Jabber function disabled
0 = Jabber function enabled
3 THIN_SEL 0, RW Thin Ethernet Select:
1 = Asserts THIN pin (pin 63)
0 = Deasserts THIN pin (pin 63)
This pin may be used as a general purpose select pin.
2 RX_FILT_DS 0, RW TPI Receive Filter Disable:
1 = Disable TPI receive filter
0 = Enable TPI receive filter
1 RESERVED 0, RO Reserved: Writes ignored, read as 0
0 RESERVED 0, RO Reserved: Writes as 0, read as 0
Table 23. PHY Control Register (PHYCTRL) Address 19h
Bit Bit Name Default Description
15 RESERVED 0, RO Reserved: Writes ignored, read as 0
14 RESERVED 0, RO Reserved: Writes ignored, read as 0
13:12 TW_EQSEL[1:0] <00>, RW TWISTER Equalization Select:
Used in combination to select the 4 equalization modes. Modes
3, 2, 1 should be accessible to external device pin for debug pur-
poses.
<11> = Equalization off
<10> = Equalization on
<01> = Adaptive Equalization
<00> = Full Adaptive Equalization
11 TW_BLW_DS 0, RW TWISTER Base Line Wander Disable:
1 = BLW Feedback loop disabled
0 = BLW Feedback loop enabled
10 RESERVED 0, RO Reserved: Writes ignored, read as 0
Table 22. 10BASE-T Control & Status Register (10BTSCR) Address 18h (Continued)
Bit Bit Name Default Description