Datasheet

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8.0 Register Block (Continued)
12 BP_SCR Strap, RW Bypass Scrambler/Descrambler Function:
This bit is set according to the strap configuration of the SYMBOL
pin or the
FXEN pin at power-up/reset. After reset this bit may be
written to by software.
1 = Scrambler and descrambler functions bypassed
0 = Normal scrambler and descrambler operation
11 BP_RX Strap, RW Bypass Receive Function:
This bit is set according to the strap configuration of the SYMBOL
pin at power-up/reset. After reset this bit may be written to by soft-
ware.
1 = Receive functions (descrambler and symbol decoding func-
tions) bypassed.
0 = Normal operation.
10 BP_TX Strap, RW Bypass Transmit Function:
This bit is set according to the strap configuration of the SYMBOL
pin at power-up/reset. After reset this bit may be written by soft-
ware.
1 = Transmit functions (symbol encoder and scrambler) by-
passed
0 = Normal operation
9:7 100_DP_CTL Strap, RW 100Mps Data Path Control Bits:
At reset, if
FXEN is true then this will default to <011>, else it will
default to <000>. These bits control the 100Mps loopback func-
tion in CorePhy as follows:
<000> Normal Mode
<001> CorePhy Loopback
<010> Reserved
<011> Normal Fiber
<100> Reserved
<101> Reserved
<110> Reserved
<111> Reserved
Note: A write to the Loopback bit (14) of the BMCR (00h) will
override the value set in this register.
6 RESERVED 0, RO Reserved: Writes as 0, read as 0
5 TW_LBEN 0, RW TWISTER Loopback Enable:
1 = TWISTER loopback
0 = Normal mode
Note: A write to the Loopback bit (14) of the BMCR (00h) will
override the value set in this register.
4 10Mb_ENDEC_LB 0, RW 10 Mb/s ENDEC Loopback:
1 = 10Mb/s ENDEC loopback
0 = Normal TREX operation
Note: A write to the Loopback bit (14) of the BMCR (00h) will
override the value set in this register.
3 RESERVED 0, RO Reserved: Writes as 0, read as 0
2 RESERVED 0, RO Reserved: Writes as 0, read as 0
Table 21. Loopback & Bypass Register (LBR) Address 17h (Continued)
Bit Bit Name Default Description