Datasheet
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8.0 Register Block (Continued)
This counter provides information required to implement the isolates attribute within the Repeater Port managed object
class of Clause 30 of the IEEE 802.3 specification.
This counter provides information required to implement the FalseCarriers attribute within the MAU managed object class
of Clause 30 of the IEEE 802.3 specification.
This counter provides information required to implement the aSymbolErrorDuringCarrier attribute within the PHY man-
aged object class of Clause 30 of the IEEE 802.3 specification.
Table 17. Disconnect Counter Register (DCR) Address 13h
Bit Bit Name Default Description
15:0 DCNT[15:0] <0000h>, RW /
COR
Disconnect Counter:
This 16 bit counter increments for each isolate event. Each time
the CIM detects a transition from the False Carrier state to the
Link Unstable state of the Carrier Integrity State Machine, the
counter increments. This counter rolls over when it reaches its
max count (FFFFh).
Table 18. False Carrier Sense Counter Register (FCSCR) Address 14h
Bit Bit Name Default Description
15:0 FCSCNT[15:0] <0000h>, RW /
COR
False Carrier Event Counter:
This 16 bit counter increments for each false carrier event. A false
carrier event occurs when carrier sense is asserted without J/K
symbol detection. This counter rolls over when it reaches its max
count (FFFFh).
Table 19. Receive Error Counter Register (RECR) Address 15h
Bit Bit Name Default Description
15:0 RXERCNT[15:0] <0000h>, RW /
COR
RX_ER Counter:
This 16 bit counter is incremented for each receive error detect-
ed. The counter is incremented when valid carrier is present and
there is at least one occurrence of an invalid data symbol. This
event can increment only once per valid carrier event. If a colli-
sion is present, this attribute will not increment. This counter rolls
over when it reaches its max count (FFFFh).
Table 20. 100 Mb/s PCS Configuration and Status Register (PCSR) Address 16h
Bit Bit Name Default Description
15 Single_SD 0, RW SIngle Ended Signal Detect Enable:
1=Single Ended SD mode enabled
0=Single Ended SD mode disabled
14 FEFI_EN Strap, RW Far End Fault Indication Mode:
1 = FEFI mode enabled
0 = FEFI mode disabled
Note: If Auto-Negotiation is enabled, bit 12 of BMCR, this bit is
RO and forced to zero. Additionally, if FX_EN is set to a one then
this bit is RO and forced to a one.
13 DESCR_TO_RST 0, RW Reset Descrambler Time-Out Counter:
1 = Reset Time-Out Counter
0 = Normal operation