Datasheet

55 www.national.com
8.0 Register Block (Continued)
This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt generation include: Link
State Change, Jabber Event, Remote Fault, Auto-Negotiation Complete or any of the counters becoming half-full. Note
that the TINT bit operates independently of the INTEN bit. In other words, INTEN does not need to be active to generate
the test interrupt.
This register implements the MII Interrupt PHY Generic Status Register.
3 Loopback Status 0, RO Loopback:
1 = Loopback enabled
0 = Normal operation
2 Duplex Status RO Duplex:
This bit indicates duplex status and is determined from Auto-Ne-
gotiation or Forced Modes.
1 = Running in Full duplex mode
0 = Running in Half duplex mode
Note: This bit is only valid if Auto-Negotiation is enabled and
complete and there is a valid link or if Auto-Negotiation is disabled
and there is a valid link.
1 Speed Status RO Speed10:
This bit indicates the status of the speed and is determined from
Auto-Negotiation or Forced Modes.
1 = Running in 10Mb/s mode
0 = Running in 100 Mb/s mode
Note: This bit is only valid if Auto-Negotiation is enabled and
complete and there is a valid link or if Auto-Negotiation is disabled
and there is a valid link.
0 Link Status 0, RO Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation)
0 = Link not established
The criteria for link validity is implementation specific.
Table 15. MII Interrupt PHY Specific Control Register (MIPSCR) Address 11h
Bit Bit Name Default Description
15:2 Reserved 0, RO Reserved: Writes ignored, Read as 0
1 INTEN 0, RW Interrupt Enable:
1 = Enable event based interrupts
0 = Disable event based interrupts
0 TINT 0, RW Test Interrupt:
Forces the PHY to always generate an interrupt to allow testing
of the interrupt.
1 = Generate an interrupt at the end of each access
0 = Do not generate interrupt
Table 16. MII Interrupt PHY Generic Status Register (MIPGSR) Address 12h
Bit Bit Name Default Description
15 MINT 0, RO/COR MII Interrupt Pending:
Indicates that an interrupt is pending and is cleared by the current
read. A read of this will also clear the MII Interrupt bit (8) of the
PHYSTS (10h) register.
14:0 Reserved 0, RO Reserved: Writes ignored, Read as 0
Table 14. PHY Status Register (PHYSTS) Address 10h
(Continued)
Bit Bit Name Default Description