Datasheet

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8.0 Register Block (Continued)
The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83843. The Identifier consists of a
concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num-
ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended
to support network management. National's IEEE assigned OUI is 080017h.
This register contains the advertised abilities of this device as they will be transmitted to its Link Partner during Auto-
Negotiation.
Table 8. PHY Identifier Register #1 (PHYIDR1) Address 02h
Bit Bit Name Default Description
15:0 OUI_MSB <00 1000 0000
0000 00>, RO/P
OUI Most Significant Bits: This register stores bits 3 to 18 of the
OUI (080017h) to bits 15 to 0 of this register respectively. The
most significant two bits of the OUI are ignored (the IEEE stan-
dard refers to these as bits 1 and 2).
Table 9. PHY Identifier Register #2 (PHYIDR2) Address 03h
Bit Bit Name Default Description
15:10 OUI_LSB <01 0111>,
RO/P
OUI Least Significant Bits:
Bits 19 to 24 of the OUI (080017h) are mapped to bits 15 to 10
of this register respectively.
9:4 VNDR_MDL <00 0001>,
RO/P
Vendor Model Number:
Six bits of vendor model number mapped to bits 9 to 4 (most sig-
nificant bit to bit 9).
3:0 MDL_REV <0000>, RO/P Model Revision Number:
Four bits of vendor model revision number mapped to bits 3 to 0
(most significant bit to bit 3). This field will be incremented for all
major device changes.
Table 10. Auto-Negotiation Advertisement Register (ANAR) Address 04h
Bit Bit Name Default Description
15 NP 0, RW Next Page Indication:
0 = Next Page Transfer not desired
1 = Next Page Transfer desired
14 Reserved 0, RO/P Reserved by IEEE: Writes ignored, Read as 0
13 RF 0, RW Remote Fault:
1 = Advertises that this device has detected a Remote Fault
0 = No Remote Fault detected
12:11 Reserved 0, RW Reserved for Future IEEE use: Write as 0, Read as 0
10 FDFC 0, RW Full Duplex Flow Control:
1 = Advertise that the DTE(MAC) has implemented both the op-
tional MAC control sublayer and the pause function as specified
in clause 31 and annex 31B of 802.3u
0= No MAC based full duplex flow control
9 T4 0, RO/P 100BASE-T4 Support:
1= 100BASE-T4 is supported by the local device
0 = 100BASE-T4 not supported
8 TX_FD Strap, RW 100BASE-TX Full Duplex Support:
1 = 100BASE-TX Full Duplex is supported by the local device
0 = 100BASE-TX Full Duplex not supported
At reset, this bit is set by AN0/AN1. After reset, this bit may be
written to by software.