Datasheet
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8.0 Register Block (Continued)
12 10BASE-T Full Du-
plex
1, RO/P 10BASE-T Full Duplex Capable:
1 = Device able to perform 10BASE-T in full duplex mode
0 = Device not able to perform 10BASE-T in full duplex mode
11 10BASE-T Half Du-
plex
1, RO/P 10BASE-T Half Duplex Capable:
1 = Device able to perform 10BASE-T in half duplex mode
0 = Device not able to perform 10BASE-T in half duplex mode
10:7 Reserved 0, RO Reserved: Write as 0, read as 0
6 Preamble
Suppression
1, RO/P Preamble suppression Capable:
1 = Device able to perform management transaction with pream-
ble suppressed*
0 = Device not able to perform management transaction with pre-
amble suppressed
* Need minimum of 32 bits of preamble after reset.
5 Auto-Negotiation
Complete
0, RO Auto-Negotiation Complete:
1 = Auto-Negotiation process complete
0 = Auto-Negotiation process not complete
4 Remote Fault 0, RO/LH Remote Fault:
1 = Remote Fault condition detected (cleared on read or by a chip
reset). Fault criteria is Far End Fault Isolation or notification from
Link Partner of Remote Fault.
0 = No remote fault condition detected
3 Auto-Negotiation
Ability
1, RO/P Auto Configuration Ability:
1 = Device is able to perform Auto-Negotiation
0 = Device is not able to perform Auto-Negotiation
2 Link Status 0, RO/L Link Status:
1 = Valid link established (for either 10 or 100 Mb/s operation)
0 = Link not established
The criteria for link validity is implementation specific. The link
status bit is implemented with a latching function, so that the oc-
currence of a link failure condition causes the Link Status bit to
become cleared and remain cleared until it is read via the man-
agement interface.
1 Jabber Detect 0, RO/L Jabber Detect:
1 = Jabber condition detected
0 = No Jabber
This bit is implemented with a latching function so that the occur-
rence of a jabber condition causes it to become set until it is
cleared by a read to this register by the management interface or
by a Device Reset. This bit only has meaning in 10 Mb/s mode.
0 Extended Capability 1, RO/P Extended Capability:
1 = Extended register capable
0 = Basic register capable only
Table 7. Basic Mode Status Register (BMSR) Address 01h
(Continued)
Bit Bit Name Default Description