Datasheet

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8.0 Register Block (Continued)
10 Isolate Strap, RW Isolate:
1 = Isolates the DP83843 from the MII with the exception of the
serial management. When this bit is asserted, the DP83843 does
not respond to TXD[3:0], TX_EN, and TX_ER inputs, and it pre-
sents a high impedance on its TX_CLK, RX_CLK, RX_DV,
RX_ER, RXD[3:0], COL and CRS outputs.
0 = Normal operation
If the PHY address is set to “00000” at power-up/reset the isolate
bit will be set to one, otherwise it defaults to 0. After reset this bit
may be written to by software.
9 Restart Auto-Negoti-
ation
0, RW/SC Restart Auto-Negotiation:
1 = Restart Auto-Negotiation. Re-initiates the Auto-Negotiation
process. If Auto-Negotiation is disabled (bit 12 of this register
cleared), this bit has no function and should be cleared. This bit
is self-clearing and will return a value of 1 until Auto-Negotiation
is initiated by the Device, whereupon it will self-clear. Operation
of the Auto-Negotiation process is not affected by the manage-
ment entity clearing this bit.
0 = Normal operation
8 Duplex Mode Strap, RW Duplex Mode:
1 = Full Duplex operation. Duplex selection is allowed when Auto-
Negotiation is disabled (bit 12 of this register is cleared).
0 = Half Duplex operation
At reset this bit is set by either AN0 or AN1. After reset this bit may
be written to by software.
7 Collision Test 0, RW Collision Test:
1 = Collision test enabled
0 = Normal operation
When set, this bit will cause the COL signal to be asserted in re-
sponse to the assertion of TX_EN within 512BT. The COL signal
will be de-asserted within 4BT in response to the de-assertion of
TX_EN.
6:0 Reserved 0, RO Reserved: Write ignored, read as zero
Table 7. Basic Mode Status Register (BMSR) Address 01h
Bit Bit Name Default Description
15 100BASE-T4 0, RO/P 100BASE-T4 Capable:
1 = Device able to perform in 100BASE-T4 mode
0 = Device not able to perform in 100BASE-T4 mode
The PHYTER is NOT capable of supporting 100BASE-T4 and
this bit is permanently set to 0.
14 100BASE-TX Full
Duplex
1, RO/P 100BASE-TX Full Duplex Capable:
1 = Device able to perform 100BASE-TX in full duplex mode
0 = Device not able to perform 100BASE-TX in full duplex mode
13 100BASE-TX Half
Duplex
1, RO/P 100BASE-TX Half Duplex Capable:
1 = Device able to perform 100BASE-TX in half duplex mode
0 = Device not able to perform 100BASE-TX in half duplex mode
Table 6. Basic Mode Control Register (BMCR) Address 00h (Continued)
Bit Bit Name Default Description