Datasheet

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8.0 Register Block
8.1 Register Definitions
Register maps and address definitions are given in the following tables:
In the register definitions under the ‘Default’ heading, the following definitions hold true:
— RW = Read/Write; Register bit is able to be read and written to by software
— RO = Read Only; Register bit is able to be read but not written to by software
— L(H) = Latch/Hold; Register bit is latched and held until read by software based upon the occurrence of the correspond-
ing event
— SC = Self Clear; Register bit will clear itself after the event has occurred without software intervention
— P = Permanent; Register bit is permanently set to the default value and no action will cause the bit to change
Table 5. Register Block - Phyter Register Map
Offset Access Tag Description
00h RW BMCR Basic Mode Control Register
01h RO BMSR Basic Mode Status Register
02h RO PHYIDR1 PHY Identifier Register #1
03h RO PHYIDR2 PHY Identifier Register #2
04h RW ANAR Auto-Negotiation Advertisement Register
05h RW ANLPAR Auto-Negotiation Link Partner Ability Register
06h RW ANER Auto-Negotiation Expansion Register
07h RW ANNPTR Auto-Negotiation Next Page TX
08h-0Fh Reserved Reserved
10h RO PHYSTS PHY Status Register
11h RW MIPSCR MII Interrupt PHY Specific Control Register
12h RO MIPGSR MII Interrupt PHY Generic Status Register
13h RW DCR Disconnect Counter Register
14h RW FCSCR False Carrier Sense Counter Register
15h RW RECR Receive Error Counter Register
16h RW PCSR PCS Sub-Layer Configuration and Status Register
17h RW LBR Loopback and Bypass Register
18h RW 10BTSCR 10BASE-T Status & Control Register
19h RW PHYCTRL PHY Control Register
1Ah-1Fh Reserved Reserved