Datasheet

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Description:
The symptoms of this problem include:
Register 1: Will show negotiation NOT complete (bit 5 = 0)
Register 6: Will show a page received, then page receive
will be cleared on read of this register (bit 1 = 1, then bit 1 =
0 if read twice)
Register 1a: Will have the data 00a3
Solution / Workaround:
The workarounds include (these are mutually exclusive):
1. Provide a 100mb data stream to the DP83843BVJE (fix
the problem)
2. Force 10mb mode by writing 0000h (half10) or 0100
(full10) to Register 0. This is a logical progression since
the 100mb side of the partner logic is down.
3. If you want to run AutoNegotiation again, with reduced
capabilities or all capabilities:
Turn off AutoNegotiation by writing a 0000h to Register 0.
(Need to do this to clear the DP83843 from sending idles.)
Change the capabilities to the desired configuration by writ-
ing to Register 4 (0061 for full10/half10, or 0021 for half10
only, etc.)
Enable AutoNegotiation by writing a 1200 to Register 0.
(This restarts AutoNegotiation as well)
7.9 Common Mode Capacitor for EMI
improvement
Type:
Informational Hardware
Problem:
As with any high-speed design it is always practical to take
precautions regarding the design and layout of a system to
attempt to ensure acceptable EMI performance.
Description:
In an attempt to improve the EMI performance of a
DP83843BVJE based PCI Node Card, a 10pF capacitor
was installed from the center-tap of the primary winding of
the transmit transformer to gnd. This common mode capac-
itive filtering improved (reduced) the EMI emissions by sev-
eral dB at critical frequencies when tested in an FCC
certified open field test site.
Solution / Workaround:
It is recommended that the footprint for a typical ceramic
chip cap be included on all new DP83843BVJE based
designs to allow for the experimentation of EMI improve-
ment. Again, a component footprint for the 10pF capacitor
should be installed from the center-tap of the primary wind-
ing of the transmit transformer to system gnd. The inclusion
of this capacitor should have no deleterious effect on the
differential signalling of the transmitted signal. In fact,
because of the unique current source transmitter of the
DP83843BVJE, this center-tap cap has been shown to
actually improve some of the signal characteristics such as
rise/fall times and transmit return loss.
When including this component in a given design, it is rec-
ommended that it be connected from the transmit trans-
former primary center-tap directly to ground with an
absolute minimum of routing (preferably just an immediate
via to the ground plane).
7.10 BAD_SSD Event Lockup
Type:
Urgent Hardware
Problem:
When the PHYTER receives a particular invalid data
sequence, it can get stuck in the RX_DATA state with an
invalid alignment. It will not recover until the link is broken
or software intervenes. The required data sequence looks
like a bad_ssd event (I,J, followed by symbol with MSB=0),
followed eventually by a good IJK pattern before seeing 10
consecutive idle bits. The data pattern also has to show up
on a specific alignment.
Description:
Root cause is that the transition from BAD_SSD state to
the CARRIER_DET state, which can only occur if there is a
single IDLE between packets, does not cause a re-loading
of the data alignment. If the Bad SSD event which pre-
ceded this met certain conditions defined above, then the
alignment logic is in an invalid state and the state machine
will not be able to detect an end of frame condition.
Solution:
There is no workaround available. Since the data pattern
should never occur on a normally operating network, it has
been decided that no corrective action is required for the
current product.