Datasheet
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resistor be placed between the TWREF pin (pin 60) and
TW_AGND. (1/10th Watt resistor with a 1% tolerance is
recommended)
7.5 Magnetics
Type:
Informational Hardware
Problem:
N/A
Description:
The DP83843BVJE has been extensively tested with the
following single package magnetics:
Valor PT4171 and ST6118
Bel Fuse S558-5999-39
Pulse H1086
Solution / Workaround:
Please note that one of the most important parameters that
is directly affected by the magnetics is 100BASE-TX Out-
put Transition Timing. Even with the Valor PT4171S mag-
netics, it is possible, depending on the system design,
layout, and associated parasitics, the output transition
times may need to be further controlled.
In order to help control the output transition time of the
100BASE-TX transmit signal, the user may wish to place a
capacitive load across the TPTD+/- pins as close to these
pins as possible. However, because every system is differ-
ent, it is suggested that the system designer experiment
with the capacitive value in order to obtain the desired
results.
Note that the board layout, the magnetics, and the output
signal of the DP83843BVJE each contribute to the final rise
and fall times as measured across the RJ45-8 transmit
pins. It should be noted that excessive capacitive loading
across the TPTD+/- pins may result in improper transmit
return loss performance at high frequencies (up to 80MHz).
Finally, when performing 100Mb/s transmit return loss
measurements, it is recommended that the DP83843BVJE
be placed in True Quiet mode as described here:
In order to configure the PHYTER for "True Quiet" opera-
tion, the following software calls should occur via the serial
MII management port following normal initialization of the
device:
- Write 01h to register 1Fh (this enables the extended
register set)
- Write 02h to register 05h (this disables the NRZI
encoder, required for True Quiet)
- write 00h to register 1Fh (this exits the extended register
set)
- Set bit 9 of register 16h (this enables TX_QUIET which
stops transmitting 100M IDLEs))
7.6 Next Page Toggle Bit Initialization
Type:
Urgent Software
Problem:
The DP83843BVJE's Next Page Toggle bit initializes to 0
independent of the value programmed in bit 11 of the
Advertised Abilities Register (ANAR), Reg 4h
Description:
The Next Page Toggle bit is used only in Next Page opera-
tions, and is used to distinguish one page from another.
The AutoNegotiation specification indicates that the toggle
bit should take on an initial value equal to that of bit 11 in
the ANAR, Reg 4h.
The DP83843BVJE incorrectly initializes this bit to 0, inde-
pendent of the setting of bit 11 in the ANAR. Note that this
bit is a RESERVED bit in the 802.3 specification, and
defaults to 0 for all combinations of strap options.
If the user were to program both the Next Page bit, bit 15,
and the RESERVED bit, bit 11, to a logic 1 to perform a
next page type negotiation, and the partner node also sup-
ported next page operation, then the negotiation would not
complete due to the initial wrong polarity of the toggle bit.
Solution / Workaround:
Do not set RESERVED bit 11 (reg 04h) to a logic 1 if you
plan to perform next page operations.
7.7 Base Page to Next Page Initial FLP Burst
Spacing
Type:
Informational Hardware
Problem:
In performing Next Page Negotiation, the FLP burst spac-
ing on the initial burst when changing from the Base Page
to the Next Page can be as long as 28ms. The 802.3u
specification, Clause 28 sets a maximum of 22.3ms. Thus,
there is a potential violation of 5.7ms.
Description:
This anomaly is due to the handshake between the arbitra-
tion and transmit state machines within the device. All other
FLP burst to burst spacings, either base page or next page,
will be in the range of 13ms to 15ms.
Note that the violating burst causes NO functional prob-
lems for either base page or next page exchange. This is
due to the fact that the nlp_test_max_timer in the receive
state machine has a minimum specification of 50ms, and
the nlp_test_min_timer has a minimum specification of
5ms. Thus, even if the transmitter waits 28ms vs. 22.3ms
between FLP bursts, the nlp_test_max_timer will not have
come close to expiring. (50 + 5 - 28) = 27ms slack time.
Solution.
NOT APPLICABLE, Not a functional problem
7.8 100Mb/s FLP Exchange Followed by Quiet
Type:
Informational Hardware
Problem:
The scenario is when the DP83843BVJE and another sta-
tion are BOTH using AutoNegotiation AND advertising
100mb full or half. If both units complete the FLP exchange
properly, but the partner does NOT send any idles (a
FAULT condition), then the DP83843BVJE will get into a
state in which it constantly sends 100mb idles and looks for
100mb idles from the partner.