Datasheet

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7.0 User Information
7.1 Link LED While in Force 100Mb/s Good Link
Type:
Information Hardware
Problem:
The Good Link LED (LED_LINK pin 39) will not assert
when the DP83843BVJE is programmed to force good link
in 100Mb/s mode. However, as long as the DP83843BVJE
is configured for forced 100BASE-X operation and good
link is forced for 100M operation, it will still be able to trans-
mit data even though the good link LED is not lit.
Description:
When the DP83843BVJE is configured for forced good link
in 100Mb/s mode, by setting bit 6 of the PCS register
(address 16h), the LINK_LED pin will not assert unless an
internal state machine term, referred to as Cipher_In_Sync
(aka CIS), is asserted. The assertion of CIS is based on
the receive descrambler either being bypassed or becom-
ing synchronized with the receive scrambled data stream.
As long as the DP83843BVJE is configured for forced
100BASE-X operation however, setting bit 6 of the PCS
register (address 16h) will allow for transmission of data.
Solution / Workaround:
In order to assert the Link LED while in Forced Good Link
100Mb/s mode, the user may select one of two options:
1: After setting bit 6 of the PCS register (address 16h), the
user may connect the DP83843BVJE to a known good far-
end link partner that is transmitting valid scrambled IDLEs.
This will assert the internal CIS term and, in turn, assert
the Link LED.
2: After setting bit 6 of the PCS register (address 16h), the
user may then assert bit 12 of the LBR register (address
17h) to bypass the scrambler/descrambler. This will assert
the internal CIS term and, in turn, assert the Link LED. The
user should then clear bit 12 of the LBR register (address
17h) to re-engage the scrambler/descrambler to allow for
normal scrambled operation while in forced good link
100Mb/s mode.
7.2 False Link Indication When in Forced 10Mb/s
Type:
Informational Hardware
Problem:
The DP83843BVJE will indicate valid link status when
forced to 10Mb/s (without Auto-Negotiation) while receiving
100BASE-TX scrambled Idles.
Description:
The DP83843BVJE can incorrectly identify 100BASE-TX
scrambled Idles being received as valid 10BASE-T energy
and consequently indicate a valid link by the assertion of
the Link LED as well as by setting the Link Status bit (bit 2)
in the BMSR (reg 01h).
Solution / Workaround:
Do not force 10Mb/s operation. Instead, use Auto-Negotia-
tion to advertise 10BASE-T full and/or half duplex (as
desired) via the ANAR register (reg 04h)
By using Auto-Negotiation and only specifying 10BASE-T
(either half or full duplex), the DP83843BVJE will recognize
the scrambled idles as a valid 100Mb/s stream, but it will
not complete the negotiation since it is not advertising
100Mb/s capability. In an application in which the user only
desires 10Mb/s operation and is being sent 100Mb/s sig-
nals, then the correct operation is to never complete the
negotiation.
7.3 10Mb/s Repeater Mode
Type:
Urgent Hardware
Problem:
The DP83843BVJE is not designed to support the use of
certain AUI attachments in repeater applications nor will it
directly support 10Mb/s repeater applications while in
10Mb/s serial or nibble mode.
Description:
When implementing repeater applications which include a
Coaxial Transceiver Interface (CTI) connected to the
DP83843 AUI interface, CRS will be asserted due to trans-
mit data because the transmit data is looped back to the
receive channel at the CTI transceiver. The assertion of
CRS during transmit will result in undue collisions at the
repeater controller.
Additionally, because there is no way to guarantee phase
alignment of the 10MHz TX_CLK between multiple
PHYTERs in a serial 10M repeater application (same is
true for 2.5MHz TX_CLK in 10Mb/s nibble mode), assum-
ing each PHYTER is referenced to a single 25MHz X1
clock signal, it is impossible to meet the input set and hold
requirements across all ports during a transmit operation.
Solution:
It is not recommended that the DP83843BVJE be used for
AUI repeater applications where the transmit data is looped
back to the receive channel at the transceiver. (i.e. CTI).
Additionally, 10M serial and nibble repeater applications
are not currently directly supported.
7.4 Resistor Value Modifications
Type:
Urgent Hardware
Problem:
To ensure optimal performance, the DP83843BVJE band-
gap reference and receive equalization reference resistor
values require updating.
Description:
The internal bandgap reference of the DP83843BVJE is
slightly offset which results in an offset in various IEEE
conformance parameters such as VOD.
The internal adaptive equalization reference bias is also
slightly offset which can result in slightly reduced maximum
cable length performance.
Solution / Workaround:
In order to set the proper internal bandgap reference, it is
recommended that the value of the resistor connected to
the BGREF pin (pin 61) be set to 4.87KΩ (1/10th Watt
resistor with a 1% tolerance is recommended). This resis-
tor should be connected between the BGREF pin and
TW_AGND.
In order to ensure maximum cable length performance for
100BASE-TX operation, it is recommended that a 70KΩ