Datasheet

4.0 Clock Architecture (Continued)
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4.2 100BASE-X Clock Recovery Module
The diagram in Figure 18 illustrates a high level block archi-
tecture of the 100BASE-X Clock Recovery circuit. The
125Mb/s serial binary receive data stream that has been
recovered by the integrated TP-PMD receiver is routed to
the input of the phase detector. A loop consisting of the
phase detector, phase error processor, digital loop filter,
phase to frequency converter, and the frequency controlled
oscillator then works to synthesize a 125 MHz clock based
on the receive data stream. This clock is used to latch the
serial data into the deserializer where the data is then con-
verted to 5-bit code groups for processing by descrambler,
code-group alignment, and code-group decoder functional
blocks.
4.3 10 Mb/s Clock Recovery Module
The diagram in Figure 19 illustrates a high level block archi-
tecture of the 10 Mb/s Clock Recovery circuit. The 10 Mb/s
serial Manchester receive data stream, from either the
10BASE-T or AUI inputs, is routed to the input of the phase
detector. A loop consisting of the phase detector, digital
loop filter, phase selector, and the frequency generator
then works to synthesize a 20 MHz clock based on the
receive data stream. This clock is used to latch the serial
data into the deserializer where the data is then optionally
converted to 4-bit code groups for presentation to the MII
as nibble wide data clocked out at 2.5 MHz. Optionally, the
deserializer can be bypassed and the 10 Mb/s data is
clocked out serially at 10 MHz.
As a function of the Phase Detector, upon recognizing an
incoming 10 Mb/s datastream, Carrier Sense (CRS) is gen-
erated for use by the MAC.
4.4 Reference Clock Connection Options
The two basic options for connecting the DP83843 to an
external reference clock consist of the use of either an
oscillator or a crystal. Figure 20 and 21 illustrate the rec-
ommended connection for the two typical options.
Figure 20. Oscillator Reference Clock Connection Diagram
Figure 21. Xtal Reference Clock Connection Diagram
X1
X2
25 MHz
Osc 50ppm
n/c
X1
X2
33pF
33pF
25 MHz
Xtal 50ppm