Datasheet

4.0 Clock Architecture (Continued)
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Figure 18. 100BASE-X Clock Recovery Module block diagram
Figure 19. 10M Manchester Clock Recovery Module block diagram
25 MHz
Phase
Detector
Divide by 2
Phase Error
Processor
Digital Loop
Filter
Phase to
Frequency
Converter
Frequency
Controlled
Oscillator
Deserializer
Frequency
Reference
From CGM
125Mb/s
Serial Data
Input
RX_CLK
RXD [4:0]
Phase
Detector
& CRS
Filter
Phase
Selector
Clk Gen
Serial /
Nibble
MUX
Deserializer
CRS
10 MHz
RX_CLK
RXD[0]
Serial Data
RXD[3:0]
2.5 MHz
RX_CLK
10 Mb/s
Serial Data
Input
Frequency
Reference
From CGM