Datasheet

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4.0 Clock Architecture
The DP83843 incorporates a sophisticated Clock Genera-
tion Module (CGM) design which allows full operation sup-
porting all modes with a single 25 MHz (± 50 ppm) CMOS
level reference clock. As depicted in Figure 17, the single
25 MHz reference serves both the 100 Mb/s and 10 Mb/s
mode clocking requirements.
The DP83843 also incorporates Clock Recovery circuitry
(CRM) which extracts the 125 MHz clock from the 125
Mb/s receive datastream present during 100BASE-TX and
100BASE-FX applications (Figure 17).
The 10 Mb/s receive clock requirements are handled by a
PLL which is tuned to extract a clock from either 10BASE-T
or AUI receive Manchester encoded data streams
(Figure 17).
4.1 Clock Generation Module (CGM)
For 100 Mb/s operation, the external 25 MHz reference is
routed to a 250 MHz voltage controlled oscillator. The high
frequency output from the oscillator is divided by two and
serves to clock out the 125Mb/s serial bit stream for
100BASE-TX and 100BASE-FX applications. The 125
MHz clock is also routed to a counter where it is divided by
5 to produce the 25 MHz TX_CLK signal for the transmit
MII. Additionally, a set of phase related 250 MHz clock sig-
nals are routed to the Clock Recovery Module (CRM)
which act as a frequency reference to ensure proper opera-
tion.
For 10 Mb/s operation, the external 25 MHz reference is
routed to a 100 MHz voltage controlled oscillator. The high
frequency output from the oscillator is divided by five and
serves to clock out the 10BASE-T or AUI serial bit stream
for 10 Mb/s applications. The 100 MHz clock is also routed
to a counter where it is divided by either eight or two to pro-
duce the 2.5 MHz or 10 MHz TX_CLK signal for the trans-
mit MII. Additionally, a set of phase related 100 MHz clock
signals are routed to the Clock Recovery Module (CRM)
which act as a frequency reference to ensure proper opera-
tion.
Figure 17. Clock Generation Module BLOCK DIAGRAM
VCO
(250 MHz)
25 MHz
input
Divide
by 2
Divide by 5
25 MHz
125 MHz serial
transmit clock
Ref Clock to CRM
VCO
(100 MHz)
Divide
by 5
20 MHz 10BASE-T
transmit clock
Ref Clock to CRM
2.5 MHz or 10 MHz
MII TX_CLK
Divide
by 8
or 2
100M CLOCKING
10M CLOCKING
MII TX_CLK