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3.0 Configuration (Continued)

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It is important to understand that while full Auto-Negotiation

with the use of Fast Link Pulse code words can interpret

and conﬁgure to support full-duplex, parallel detection can

not recognize the difference between full and half-duplex

from a ﬁxed 10 Mb/s or 100 Mb/s link partner over twisted

pair. Therefore, as speciﬁed in 802.3u, if a far-end link part-

ner is transmitting forced full duplex 100BASE-TX for

example, the parallel detection state machine in the receiv-

ing station would be unable to detect the full duplex capa-

bility of the far-end link partner and would negotiate to a

half duplex 100BASE-TX conﬁguration (same scenario for

10 Mb/s).

3.4 100 Mb/s Symbol Mode

In Symbol mode, all of the conditioning blocks in the trans-

mit and receive sections of the 100BASE-X section are

bypassed. The 100BASE-X serial data received at the

RD+/− inputs of the DP83843 are recovered by the inte-

grated PMD receiver, shifted into 5-bit parallel words and

presented to the MII receive outputs RXD[3:0] and

RX_ER/RXD[4]. All data, including Idles, passes through

the DP83843 unaltered other than for serial/parallel conver-

sions.

Similarly, the TX_ER input pin is conﬁgured as the new

MSB (TXD[4]) to support the unaligned 5 bit transmit data.

All data, including Idles, passes through the DP83843 unal-

tered other than for serial/parallel conversions.

While in Symbol mode RX_DV and COL are held low and

TX_ER is used as the ﬁfth bit and no longer functions as

TX_ER. Additionally, the CRS output reports the state of

signal detect as generated internally for 100BASE-TX and

externally for 100BASE-FX.

Symbol mode can be used for those applications where the

system design requires only the integrated PMD, clock

recovery, and clock generation functions of the DP83843.

This is accomplished either by conﬁguring the CRS/

SYM-

BOL pin (pin 22) of the DP83843 to a logic low level prior to

power-up/reset or by setting bits 10 and 11 (BP_TX and

BP_RX respectively) of the LBR register (address 17h)

through the serial MII port. Symbol mode only applies to

100BASE-X operation.

3.5 100BASE-FX Mode

The DP83843 will allow 100BASE-FX functionality by

bypassing the scrambler and descrambler and routing the

PECL serial transmit and receive data through the separate

FXTD/AUITD outputs and FXRD/AUIRD inputs respec-

tively. Additionally, the signal detect indication from the opti-

cal transceiver is handled by the FXSD inputs. Placing the

DP83843 in 100BASE-FX mode disables the TPTD and

TPRD transmit and receive pin pairs.

Conﬁguring the DP83843 for 100BASE-FX mode can be

accomplished either through hardware conﬁguration or via

software.

The hardware conﬁguration is set simply by tying the

COL/

FXEN pin (21) to a logic low level prior to power-

on/reset. The software setting is accomplished by setting

the BP_SCR bit (bit 12) of the LBR register (address 17h)

via MII serial management.

The DP83843 can support either half-duplex or full-duplex

operation while in 100BASE-FX mode. Additionally, all MII

signaling remains identical to that of 100BASE-TX opera-

tion.

Please refer to Section 2.2 for more information regarding

100BASE-FX operation.

3.6 10 Mb/s Serial Mode

The DP83843 allows for serial MII operation. In this mode,

the transmit and receive MII data transactions occur seri-

ally at a 10 MHz clock rate on the least signiﬁcant bits

(RXD[0] and TXD[0]) of the MII data pins. This mode is

intended for use with a MAC based on a 10 Mb/s serial

interface.

While the MII control signals (CRS, RX_DV, TX_DV, and

TX_EN) as well as RX_EN and Collision are still used dur-

ing 10 Mb/s Serial mode, some of the timing parameters

are different. Refer to Section 8 for AC timing details.

Both 10BASE-T and AUI can be conﬁgured for Serial

mode. Serial mode is not supported for 100 Mb/s opera-

tion.

Serial mode can be selected via hardware by forcing the

SERIAL10 pin (pin 69) to a logic low level prior to power-

up/reset. The state of the

SERIAL10 pin is latched into bits

11 and 12 of the 10BTSCR register (address 18h) as a

result of power-up/reset. These bits can be written through

software to control serial mode operation.

While in 10 Mb/s serial mode, RXD[3:1] will be placed in

TRI-STATE mode and RX_DV asserts coincident with CRS.

3.7 10 Mb/s AUI Mode

Placing the DP83843 in AUI mode enables the

FXTD/AUITD, FXRD/AUIRD, and FXSD/CD pin pairs to

allow for any AUI compliant external transceivers to be con-

nected to the AUI interface. Placing the DP83843 in 10

Mb/s AUI mode disables the TPTD and TPRD transmit and

receive pin pairs.

The DP83843 also incorporates a THIN output control pin

for use with traditional AUI based CTI transceivers. This

output follows the state of bit 3 in the 10BTSCR register

accessible through the serial MII.

The AUI/TP autoswitching allows transceiver autoswitching

between the AUI and TP outputs. At power up, the

autoswitch function is deselected in the 10BTSCR register

(bit 9 = 0) and the current mode, AUI or TP, is reported by

the bit 13 of the 10BTSCR register (low for TPI and high for

AUI).

When the auto-switch function is enabled (bit 9 = 1), it

allows the transceiver to automatically switch between TPI

and AUI I/O’s. If there is an absence of link pulses, the

transceiver switches to AUI mode. Similarly, when the

transceiver starts detecting link pulses, it switches to TP

mode. Switching from one mode to the other is done only

after the current packet has been transmitted or received. If

the twisted pair output is jabbering and it gets into link fail

state, then the switch to AUI mode is done only after the

jabbering has stopped, including the time it takes to unjab

(unjab time). Also, if TPI mode is selected, transmit packet

data are driven only by the TPI outputs and the AUI trans-

mit outputs remain idle. Similar behavior applies when AUI

mode is selected. The only difference in AUI mode is that

the TP drivers continue to send link pulses; however, no

packet data is transmitted. The TPI receive circuitry and

the Link Integrity state machine are always active to enable

this algorithm to function as described above.