Datasheet

3.0 Configuration (Continued)
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that while an address selection of all zeros <00000> will
result in PHY Isolate mode, this will not effect serial man-
agement access.
The state of each of the PHYAD inputs are latched into the
PHYCTRL register bits [4:0] (address 19h) at system
power-up/reset depending on whether a pull-up or pull-
down resistor has been installed for each pin. For further
detail relating to the latch-in timing requirements of the
PHY Address pins, as well as the other hardware configu-
ration pins, refer to the Reset summary in Section 5.
Since the PHYAD strap options share the LED output pins,
the external components required for strapping and LED
usage must be considered in order to avoid contention.
Additionally, the sensing and auto polarity feature of the
LED must be taken into account.
Specifically, these LED outputs can be used to drive LEDs
directly, or can be used to provide status information to a
network management device. The active state of each LED
output driver is dependent on the logic level sampled by the
corresponding PHYAD input upon power-up / reset. For
example, if a given PHYAD input is resistively pulled low
(nominal 10 kΩ resistor recommended) then the corre-
sponding LED output will be configured as an active high
driver. Conversely, if a given PHYAD input is resistively
pulled high, then the corresponding LED output will be con-
figured as an active low driver. Refer to Figure 16 for an
example of LED & PHYAD connection to external compo-
nents where, in this example, the PHYAD strapping results
in address 00011 or hex 03h or decimal 3.
The adaptive nature of the LED outputs helps to simplify
potential implementation issues of these dual purpose
pins.
Refer to the PHYCTRL register (address 19h) bits [8:6] for
further information regarding LED operations and configu-
ration.
3.3 Half Duplex vs. Full Duplex
The DP83843 supports both half and full duplex operation
at both 10 Mb/s and 100 Mb/s speeds.
Half-duplex is the standard, traditional mode of operation
which relies on the CSMA/CD protocol to handle collisions
and network access. In Half-Duplex mode, CRS responds
to both transmit and receive activity in order to maintain
compliant to the IEEE 802.3 specification.
Since the DP83843 is architected to support simultaneous
transmit and receive activity it is capable of supporting full-
duplex switched applications with an aggregate throughput
of up to 200 Mb/s when operating in 100BASE-X mode.
Because the CSMA/CD protocol does not apply to full-
duplex operation, the DP83843 simply disables its own
internal collision sensing and reporting functions and modi-
fies the behavior of Carrier Sense (CRS) such that it indi-
cates only receive activity to allow the full-duplex capable
MAC to operate properly.
All modes of operation (100BASE-TX, 100BASE-FX,
10BASE-T (both nibble and serial)) can run full-duplex
although it should be noted that full-duplex operation does
not apply to typical repeater implementations or AUI appli-
cations. Additionally, other than CRS and Collision report-
ing, all remaining MII signaling remains the same
regardless of the selected duplex mode.
Figure 16. PHYAD Strapping and LED Loading Example
LED_COL/PHYAD[0]
LED_TX/PHYAD[1] LED_RX/PHYAD[2]
LED_LINK/PHYAD[3]
LED_FDPOL/PHYAD[4]
V
CC
V
CC
1 κΩ
10 κΩ 10 κΩ
1 κΩ
10 κΩ
1 κΩ
10 κΩ
1 κΩ
10 κΩ
1 κΩ