Datasheet

3.0 Configuration (Continued)
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Auto-Negotiation Priority Resolution:
— (1) 100BASE-TX Full Duplex (Highest Priority)
— (2) 100BASE-TX Half Duplex
— (3) 10BASE-T Full Duplex
— (4) 10BASE-T Half Duplex (Lowest Priority)
The Basic Mode Control Register (BMCR) at address 00h
provides control of enabling, disabling, and restarting of the
Auto-Negotiation function. When Auto-Negotiation is dis-
abled the Speed Selection bit in the BMCR (bit 13, register
address 00h) controls switching between 10 Mb/s or 100
Mb/s operation, while the Duplex Mode bit (bit 8, register
address 00h) controls switching between full duplex opera-
tion and half duplex operation. The Speed Selection and
Duplex Mode bits have no effect on the mode of operation
when the Auto-Negotiation Enable bit (bit 12, register
address 00h) is set.
The Basic Mode Status Register (BMSR) at address 01h
indicates the set of available abilities for technology types
(bits 15 to 11, register address 01h), Auto-Negotiation abil-
ity (bit 3, register address 01h), and Extended Register
Capability (bit 0, register address 01h). These bits are per-
manently set to indicate the full functionality of the
DP83843 (only the 100BASE-T4 bit is not set since the
DP83843 does not support that function, while it does sup-
port all the other functions).
The BMSR also provides status on:
— Whether Auto-Negotiation is complete (bit 5, register ad-
dress 01h)
— Whether the Link Partner is advertising that a remote
fault has occurred (bit 4, register address 01h)
— Whether a valid link has been established (bit 2, register
address 01h)
— Support for Management Frame Preamble suppression
(bit 6, register address 01h)
The Auto-Negotiation Advertisement Register (ANAR) at
address 04h indicates the Auto-Negotiation abilities to be
advertised by the DP83843. All available abilities are trans-
mitted by default, but any ability can be suppressed by writ-
ing to the ANAR. Updating the ANAR to suppress an ability
is one way for a management agent to change (force) the
technology that is used.
The Auto-Negotiation Link Partner Ability Register
(ANLPAR)at address 05h is used to receive the base link
code word as well as all next page code words during the
negotiation. Furthermore, the ANLPAR will be updated to
either 0081h or 0021h for parallel detection to either 100
Mb/s or 10 Mb/s respectively.
If Next Page is NOT being used, then the ANLPAR will
store the base link code word (link partner's abilities) and
retain this information from the time the page is received,
as indicated by a 1 in bit 1 of the Auto-Negotiation Expan-
sion Register (ANER, register address 06h), through the
end of the negotiation and beyond.
When using the next page operation, the DP83843 cannot
wait for Auto-Negotiation to complete in order to read the
ANLPAR because the register is used to store both the
Table 3. Auto-Negotiation Mode Select
AN1
(Pin 3)
AN0
(Pin 4)
Action Mode
FORCED MODES
0 M PHYSTS (10h) Bit 9 = 0, Bit 1 = 1, Bit 2 = 0
ANAR (04h) [8:0] = 021h
10BASE-T, Half-Duplex without Auto-Negotiation
1 M PHYSTS (10h) Bit 9 = 0, Bit 1 = 1, Bit 2 = 1
ANAR (04h) [8:0] = 041h
10BASE-T, Full Duplex without Auto-Negotiation
M 0 PHYSTS (10h) Bit 9 = 0, Bit 1 = 0, Bit 2 = 0
ANAR (04h) [8:0] = 081h
100BASE-X, Half-Duplex without Auto-Negotia-
tion
M 1 PHYSTS (10h) Bit 9 = 0, Bit1 = 0, Bit 2 = 1
ANAR (04h) [8:0] = 101h
100BASE-X, Full Duplex without Auto-Negotia-
tion
ADVERTISED MODES
M M PHYSTS (10h) Bit 9 = 1
ANAR (04h) [8:0] = 1E1h
All capable (i.e. Half-Duplex & Full Duplex for
10BASE-T and 100BASE-TX) advertised via
Auto-Negotiation
0 0 PHYSTS (10h) Bit 9 = 1
ANAR (04h) [8:0] = 061h
10BASE-T, Half-Duplex & Full Duplex advertised
via Auto-Negotiation
0 1 PHYSTS (10h) Bit 9 = 1
ANAR (04h) [8:0] = 181h
100BASE-TX, Half-Duplex & Full Duplex adver-
tised via Auto-Negotiation
1 0 PHYSTS (10h) Bit 9 = 1
ANAR (04h) [8:0] = 0A1h
10BASE-T & 100BASE-TX, Half-Duplex adver-
tised via Auto-Negotiation
1 1 PHYSTS (10h) Bit 9 = 1
ANAR (04h) [8:0] = 021h
10 BASE-T, Half-Duplex advertised via Auto-Ne-
gotiation.
Note: “M” indicates logic mid level (V
cc
/2), “1” indicates logic high level, “0” indicates logic low level.